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| author | Xiaojuan Yang | 2022-07-05 08:49:00 +0200 |
|---|---|---|
| committer | Richard Henderson | 2022-07-05 12:55:17 +0200 |
| commit | ddf93261847df55137436abe429aae7f9d8228dd (patch) | |
| tree | df643314296f894d227ac269bfac43ec7df7d037 /hw/loongarch | |
| parent | tcg/tci: Remove CONFIG_DEBUG_TCG_INTERPRETER (diff) | |
| download | qemu-ddf93261847df55137436abe429aae7f9d8228dd.tar.gz qemu-ddf93261847df55137436abe429aae7f9d8228dd.tar.xz qemu-ddf93261847df55137436abe429aae7f9d8228dd.zip | |
hw/intc/loongarch_ipi: Fix ipi device access of 64bits
In general loongarch ipi device, 32bit registers is emulated, however for
anysend/mailsend device only 64bit register access is supported. So separate
the ipi memory region into two regions, including 32 bits and 64 bits.
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Message-Id: <20220705064901.2353349-2-yangxiaojuan@loongson.cn>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'hw/loongarch')
| -rw-r--r-- | hw/loongarch/loongson3.c | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/hw/loongarch/loongson3.c b/hw/loongarch/loongson3.c index 403dd91e11..15fddfc4f5 100644 --- a/hw/loongarch/loongson3.c +++ b/hw/loongarch/loongson3.c @@ -230,7 +230,10 @@ static void loongarch_irq_init(LoongArchMachineState *lams) /* IPI iocsr memory region */ memory_region_add_subregion(&env->system_iocsr, SMP_IPI_MAILBOX, sysbus_mmio_get_region(SYS_BUS_DEVICE(ipi), - cpu)); + cpu * 2)); + memory_region_add_subregion(&env->system_iocsr, MAIL_SEND_ADDR, + sysbus_mmio_get_region(SYS_BUS_DEVICE(ipi), + cpu * 2 + 1)); /* extioi iocsr memory region */ memory_region_add_subregion(&env->system_iocsr, APIC_BASE, sysbus_mmio_get_region(SYS_BUS_DEVICE(extioi), |