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| author | Jonathan Cameron | 2022-04-29 16:40:38 +0200 |
|---|---|---|
| committer | Michael S. Tsirkin | 2022-05-13 12:13:36 +0200 |
| commit | abb3009baf90e5984ff1c230af0bc92a45e64864 (patch) | |
| tree | 64dc0af747f36a82600d2ccc18deb2410f804e48 /hw/mem/meson.build | |
| parent | hw/pci/cxl: Create a CXL bus type (diff) | |
| download | qemu-abb3009baf90e5984ff1c230af0bc92a45e64864.tar.gz qemu-abb3009baf90e5984ff1c230af0bc92a45e64864.tar.xz qemu-abb3009baf90e5984ff1c230af0bc92a45e64864.zip | |
cxl: Machine level control on whether CXL support is enabled
There are going to be some potential overheads to CXL enablement,
for example the host bridge region reserved in memory maps.
Add a machine level control so that CXL is disabled by default.
Signed-off-by: Jonathan Cameron <jonathan.cameron@huawei.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20220429144110.25167-14-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Diffstat (limited to 'hw/mem/meson.build')
0 files changed, 0 insertions, 0 deletions