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| author | Philippe Mathieu-Daudé | 2022-10-26 21:18:19 +0200 |
|---|---|---|
| committer | Philippe Mathieu-Daudé | 2022-10-31 11:32:45 +0100 |
| commit | 36d7487b2aa033e9792fb310c39d106ffcadaa4f (patch) | |
| tree | 645b52ba691ecff5ac56610af00d4fdf4cdbfa1b /hw/mips/bootloader.c | |
| parent | hw/mips/boston: Don't set link_up for xilinx-pcie (diff) | |
| download | qemu-36d7487b2aa033e9792fb310c39d106ffcadaa4f.tar.gz qemu-36d7487b2aa033e9792fb310c39d106ffcadaa4f.tar.xz qemu-36d7487b2aa033e9792fb310c39d106ffcadaa4f.zip | |
hw/mips/bootloader: Allow bl_gen_jump_kernel to optionally set register
When one of the $sp/$a[0..3] register is already set, we might
want bl_gen_jump_kernel() to NOT set it again. Pass a boolean
argument for each register, to allow to optionally set them.
Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20221026191821.28167-2-philmd@linaro.org>
Diffstat (limited to 'hw/mips/bootloader.c')
| -rw-r--r-- | hw/mips/bootloader.c | 28 |
1 files changed, 21 insertions, 7 deletions
diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c index 99991f8b2b..f5f42f2bf2 100644 --- a/hw/mips/bootloader.c +++ b/hw/mips/bootloader.c @@ -165,15 +165,29 @@ void bl_gen_jump_to(uint32_t **p, target_ulong jump_addr) bl_gen_nop(p); /* delay slot */ } -void bl_gen_jump_kernel(uint32_t **p, target_ulong sp, target_ulong a0, - target_ulong a1, target_ulong a2, target_ulong a3, +void bl_gen_jump_kernel(uint32_t **p, + bool set_sp, target_ulong sp, + bool set_a0, target_ulong a0, + bool set_a1, target_ulong a1, + bool set_a2, target_ulong a2, + bool set_a3, target_ulong a3, target_ulong kernel_addr) { - bl_gen_load_ulong(p, BL_REG_SP, sp); - bl_gen_load_ulong(p, BL_REG_A0, a0); - bl_gen_load_ulong(p, BL_REG_A1, a1); - bl_gen_load_ulong(p, BL_REG_A2, a2); - bl_gen_load_ulong(p, BL_REG_A3, a3); + if (set_sp) { + bl_gen_load_ulong(p, BL_REG_SP, sp); + } + if (set_a0) { + bl_gen_load_ulong(p, BL_REG_A0, a0); + } + if (set_a1) { + bl_gen_load_ulong(p, BL_REG_A1, a1); + } + if (set_a2) { + bl_gen_load_ulong(p, BL_REG_A2, a2); + } + if (set_a3) { + bl_gen_load_ulong(p, BL_REG_A3, a3); + } bl_gen_jump_to(p, kernel_addr); } |