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| author | Leon Alrae | 2016-03-15 10:59:29 +0100 |
|---|---|---|
| committer | Leon Alrae | 2016-03-30 10:13:59 +0200 |
| commit | a9bd9b5a8682c8129b46ae0e673efdad35f493c2 (patch) | |
| tree | b3fac509c0219513c0761958708f938ce5504113 /hw/mips/cps.c | |
| parent | hw/mips: add initial Global Config Register support (diff) | |
| download | qemu-a9bd9b5a8682c8129b46ae0e673efdad35f493c2.tar.gz qemu-a9bd9b5a8682c8129b46ae0e673efdad35f493c2.tar.xz qemu-a9bd9b5a8682c8129b46ae0e673efdad35f493c2.zip | |
hw/mips/cps: create GCR block inside CPS
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
Diffstat (limited to 'hw/mips/cps.c')
| -rw-r--r-- | hw/mips/cps.c | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/hw/mips/cps.c b/hw/mips/cps.c index a74df46f9b..e77b1da507 100644 --- a/hw/mips/cps.c +++ b/hw/mips/cps.c @@ -62,6 +62,8 @@ static void mips_cps_realize(DeviceState *dev, Error **errp) CPUMIPSState *env; MIPSCPU *cpu; int i; + Error *err = NULL; + target_ulong gcr_base; for (i = 0; i < s->num_vp; i++) { cpu = cpu_mips_init(s->cpu_model); @@ -76,6 +78,27 @@ static void mips_cps_realize(DeviceState *dev, Error **errp) cpu_mips_clock_init(env); qemu_register_reset(main_cpu_reset, cpu); } + + cpu = MIPS_CPU(first_cpu); + env = &cpu->env; + + /* Global Configuration Registers */ + gcr_base = env->CP0_CMGCRBase << 4; + + object_initialize(&s->gcr, sizeof(s->gcr), TYPE_MIPS_GCR); + qdev_set_parent_bus(DEVICE(&s->gcr), sysbus_get_default()); + + object_property_set_int(OBJECT(&s->gcr), s->num_vp, "num-vp", &err); + object_property_set_int(OBJECT(&s->gcr), 0x800, "gcr-rev", &err); + object_property_set_int(OBJECT(&s->gcr), gcr_base, "gcr-base", &err); + object_property_set_bool(OBJECT(&s->gcr), true, "realized", &err); + if (err != NULL) { + error_propagate(errp, err); + return; + } + + memory_region_add_subregion(&s->container, gcr_base, + sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gcr), 0)); } static Property mips_cps_properties[] = { |