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| author | Philippe Mathieu-Daudé | 2021-03-04 19:25:11 +0100 |
|---|---|---|
| committer | Philippe Mathieu-Daudé | 2021-03-13 20:29:36 +0100 |
| commit | 8d492c5f06e107b2f7ebeb66ccb25537cccbf269 (patch) | |
| tree | 14ea6fcc5a2212679575c6b3c1471834f3e9bd32 /hw/mips/gt64xxx_pci.c | |
| parent | hw/mips/gt64xxx: Initialize ISD I/O memory region in DeviceRealize() (diff) | |
| download | qemu-8d492c5f06e107b2f7ebeb66ccb25537cccbf269.tar.gz qemu-8d492c5f06e107b2f7ebeb66ccb25537cccbf269.tar.xz qemu-8d492c5f06e107b2f7ebeb66ccb25537cccbf269.zip | |
hw/mips/gt64xxx: Simplify ISD MemoryRegion read/write handlers
The ISD MemoryRegion is implemented for 32-bit accesses.
Simplify it by setting the MemoryRegionOps::impl min/max
access size fields.
Since the region is registered with a size of 0x1000 bytes,
we can remove the hwaddr mask.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: BALATON Zoltan <balaton@eik.bme.hu>
Message-Id: <20210309142630.728014-3-f4bug@amsat.org>
Diffstat (limited to 'hw/mips/gt64xxx_pci.c')
| -rw-r--r-- | hw/mips/gt64xxx_pci.c | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/hw/mips/gt64xxx_pci.c b/hw/mips/gt64xxx_pci.c index 6eb73e7705..99b1690af1 100644 --- a/hw/mips/gt64xxx_pci.c +++ b/hw/mips/gt64xxx_pci.c @@ -385,13 +385,12 @@ static void gt64120_writel(void *opaque, hwaddr addr, { GT64120State *s = opaque; PCIHostState *phb = PCI_HOST_BRIDGE(s); - uint32_t saddr; + uint32_t saddr = addr >> 2; if (!(s->regs[GT_CPU] & 0x00001000)) { val = bswap32(val); } - saddr = (addr & 0xfff) >> 2; switch (saddr) { /* CPU Configuration */ @@ -695,9 +694,8 @@ static uint64_t gt64120_readl(void *opaque, GT64120State *s = opaque; PCIHostState *phb = PCI_HOST_BRIDGE(s); uint32_t val; - uint32_t saddr; + uint32_t saddr = addr >> 2; - saddr = (addr & 0xfff) >> 2; switch (saddr) { /* CPU Configuration */ @@ -976,6 +974,10 @@ static const MemoryRegionOps isd_mem_ops = { .read = gt64120_readl, .write = gt64120_writel, .endianness = DEVICE_NATIVE_ENDIAN, + .impl = { + .min_access_size = 4, + .max_access_size = 4, + }, }; static int gt64120_pci_map_irq(PCIDevice *pci_dev, int irq_num) |