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| author | Philippe Mathieu-Daudé | 2020-12-04 23:16:45 +0100 |
|---|---|---|
| committer | Philippe Mathieu-Daudé | 2020-12-13 20:26:02 +0100 |
| commit | 07741e67542d061b45628a5de60637b006ca2de5 (patch) | |
| tree | bd41aa3ae517b298e95b7046fd4379939986e372 /hw/mips/malta.c | |
| parent | hw/mips/malta: Do not initialize MT registers if MT ASE absent (diff) | |
| download | qemu-07741e67542d061b45628a5de60637b006ca2de5.tar.gz qemu-07741e67542d061b45628a5de60637b006ca2de5.tar.xz qemu-07741e67542d061b45628a5de60637b006ca2de5.zip | |
hw/mips/malta: Rewrite CP0_MVPConf0 access using deposit()
PTC field has 8 bits, PVPE has 4. We plan to use the
"hw/registerfields.h" API with MIPS CPU definitions
(target/mips/cpu.h). Meanwhile we use magic 8 and 4.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201204222622.2743175-6-f4bug@amsat.org>
Diffstat (limited to 'hw/mips/malta.c')
| -rw-r--r-- | hw/mips/malta.c | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/hw/mips/malta.c b/hw/mips/malta.c index f06cb90a44..366f4fdfcd 100644 --- a/hw/mips/malta.c +++ b/hw/mips/malta.c @@ -24,6 +24,7 @@ #include "qemu/osdep.h" #include "qemu/units.h" +#include "qemu/bitops.h" #include "qemu-common.h" #include "qemu/datadir.h" #include "cpu.h" @@ -1136,8 +1137,11 @@ static void malta_mips_config(MIPSCPU *cpu) CPUState *cs = CPU(cpu); if (ase_mt_available(env)) { - env->mvp->CP0_MVPConf0 |= ((smp_cpus - 1) << CP0MVPC0_PVPE) | - ((smp_cpus * cs->nr_threads - 1) << CP0MVPC0_PTC); + env->mvp->CP0_MVPConf0 = deposit32(env->mvp->CP0_MVPConf0, + CP0MVPC0_PTC, 8, + smp_cpus * cs->nr_threads - 1); + env->mvp->CP0_MVPConf0 = deposit32(env->mvp->CP0_MVPConf0, + CP0MVPC0_PVPE, 4, smp_cpus - 1); } } |