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| author | Peter Maydell | 2014-06-20 20:25:17 +0200 |
|---|---|---|
| committer | Peter Maydell | 2014-06-20 20:25:18 +0200 |
| commit | d70a319b8d6f10ad895f05bdd5160cdb42f5058a (patch) | |
| tree | b2d0d547bb67a573422ccf509c1e95ba01430dde /hw/mips/mips_int.c | |
| parent | Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging (diff) | |
| parent | hw/mips: malta: Don't boot from flash with KVM T&E (diff) | |
| download | qemu-d70a319b8d6f10ad895f05bdd5160cdb42f5058a.tar.gz qemu-d70a319b8d6f10ad895f05bdd5160cdb42f5058a.tar.xz qemu-d70a319b8d6f10ad895f05bdd5160cdb42f5058a.zip | |
Merge remote-tracking branch 'remotes/kvm/uq/master' into staging
* remotes/kvm/uq/master:
hw/mips: malta: Don't boot from flash with KVM T&E
MAINTAINERS: Add entry for MIPS KVM
target-mips: Enable KVM support in build system
hw/mips: malta: Add KVM support
hw/mips: In KVM mode, inject IRQ2 (I/O) interrupts via ioctls
target-mips: Call kvm_mips_reset_vcpu() from mips_cpu_reset()
target-mips: kvm: Add main KVM support for MIPS
kvm: Allow arch to set sigmask length
target-mips: get_physical_address: Add KVM awareness
target-mips: get_physical_address: Add defines for segment bases
hw/mips: Add API to convert KVM guest KSEG0 <-> GPA
hw/mips/cputimer: Don't start periodic timer in KVM mode
target-mips: Reset CPU timer consistently
KVM: Fix GSI number space limit
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/mips/mips_int.c')
| -rw-r--r-- | hw/mips/mips_int.c | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/hw/mips/mips_int.c b/hw/mips/mips_int.c index 7dbd24d3d6..d740046ba1 100644 --- a/hw/mips/mips_int.c +++ b/hw/mips/mips_int.c @@ -23,6 +23,8 @@ #include "hw/hw.h" #include "hw/mips/cpudevs.h" #include "cpu.h" +#include "sysemu/kvm.h" +#include "kvm_mips.h" static void cpu_mips_irq_request(void *opaque, int irq, int level) { @@ -35,8 +37,17 @@ static void cpu_mips_irq_request(void *opaque, int irq, int level) if (level) { env->CP0_Cause |= 1 << (irq + CP0Ca_IP); + + if (kvm_enabled() && irq == 2) { + kvm_mips_set_interrupt(cpu, irq, level); + } + } else { env->CP0_Cause &= ~(1 << (irq + CP0Ca_IP)); + + if (kvm_enabled() && irq == 2) { + kvm_mips_set_interrupt(cpu, irq, level); + } } if (env->CP0_Cause & CP0Ca_IP_mask) { |
