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| author | Green Wan | 2020-10-20 05:37:31 +0200 |
|---|---|---|
| committer | Alistair Francis | 2020-10-22 21:00:46 +0200 |
| commit | a54d259157e2575b69e2cf7cf03592c74559cb7e (patch) | |
| tree | 4360abfcffc7237a2fc593abec5d58a6c983adff /hw/misc/arm_integrator_debug.c | |
| parent | target/riscv: raise exception to HS-mode at get_physical_address (diff) | |
| download | qemu-a54d259157e2575b69e2cf7cf03592c74559cb7e.tar.gz qemu-a54d259157e2575b69e2cf7cf03592c74559cb7e.tar.xz qemu-a54d259157e2575b69e2cf7cf03592c74559cb7e.zip | |
hw/misc/sifive_u_otp: Add write function and write-once protection
- Add write operation to update fuse data bit when PWE bit is on.
- Add array, fuse_wo, to store the 'written' status for all bits
of OTP to block the write operation.
Signed-off-by: Green Wan <green.wan@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Tested-by: Bin Meng <bin.meng@windriver.com>
Message-id: 20201020033732.12921-2-green.wan@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'hw/misc/arm_integrator_debug.c')
0 files changed, 0 insertions, 0 deletions