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| author | Philippe Mathieu-Daudé | 2022-10-30 23:38:49 +0100 |
|---|---|---|
| committer | Philippe Mathieu-Daudé | 2022-11-08 01:04:29 +0100 |
| commit | 30dd5ff892d2f51025a5fd6be55f44d9506c7df8 (patch) | |
| tree | 11d5dca170bbb2e8fbad4407fbcaa90b3dd0cf49 /hw/misc/aspeed_sbc.c | |
| parent | disas/nanomips: Tidy read for 48-bit opcodes (diff) | |
| download | qemu-30dd5ff892d2f51025a5fd6be55f44d9506c7df8.tar.gz qemu-30dd5ff892d2f51025a5fd6be55f44d9506c7df8.tar.xz qemu-30dd5ff892d2f51025a5fd6be55f44d9506c7df8.zip | |
MAINTAINERS: Inherit from nanoMIPS
6 months ago Stefan Pejic stepped in as nanoMIPS maintainer
(see commit a 8e0e23445a "target/mips: Undeprecate nanoMIPS
ISA support in QEMU"), however today his email is bouncing:
** Message blocked **
Your message to stefan.pejic@syrmia.com has been blocked. See technical details below for more information.
The response from the remote server was:
550 5.4.1 Recipient address rejected: Access denied. AS(201806281) [DBAEUR03FT030.eop-EUR03.prod.protection.outlook.com]
To avoid unmaintained code, I feel forced to merge this code
back with the generic MIPS section.
Historical references:
- https://lore.kernel.org/qemu-devel/TY0PR03MB679726901BD6C6BE40114A2FE2A79@TY0PR03MB6797.apcprd03.prod.outlook.com/
- https://lore.kernel.org/qemu-devel/b858a20e97b74e7b90a94948314d0008@MTKMBS62N2.mediatek.inc/
Cc: Vince Del Vecchio <Vince.DelVecchio@mediatek.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <49f41916-687f-b9e5-2de7-9c658fe0d4c7@linaro.org>
Tested-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20221101114458.25756-6-philmd@linaro.org>
Diffstat (limited to 'hw/misc/aspeed_sbc.c')
0 files changed, 0 insertions, 0 deletions