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| author | Peter Maydell | 2020-09-14 17:03:08 +0200 |
|---|---|---|
| committer | Peter Maydell | 2020-09-14 17:03:08 +0200 |
| commit | 2d2c73d0e3d504a61f868e46e6abd5643f38091b (patch) | |
| tree | c4d2919e4a72d08810d3ebcbc3b487eb73165844 /hw/misc/trace-events | |
| parent | Merge remote-tracking branch 'remotes/philmd-gitlab/tags/edk2-next-20200914' ... (diff) | |
| parent | tests/acceptance: console boot tests for quanta-gsj (diff) | |
| download | qemu-2d2c73d0e3d504a61f868e46e6abd5643f38091b.tar.gz qemu-2d2c73d0e3d504a61f868e46e6abd5643f38091b.tar.xz qemu-2d2c73d0e3d504a61f868e46e6abd5643f38091b.zip | |
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20200914-1' into staging
* hw/misc/a9scu: Do not allow invalid CPU count
* hw/misc/a9scu: Minor cleanups
* hw/timer/armv7m_systick: assert that board code set system_clock_scale
* decodetree: Improve identifier matching
* target/arm: Clean up neon fp insn size field decode
* target/arm: Remove KVM support for 32-bit Arm hosts
* hw/arm/mps2: New board models mps2-an386, mps2-an500
* Deprecate Unicore32 port
* Deprecate lm32 port
* target/arm: Count PMU events when MDCR.SPME is set
* hw/arm: versal-virt: Correct the tx/rx GEM clocks
* New Nuvoton iBMC board models npcm750-evb, quanta-gsj
# gpg: Signature made Mon 14 Sep 2020 16:02:06 BST
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* remotes/pmaydell/tags/pull-target-arm-20200914-1: (32 commits)
tests/acceptance: console boot tests for quanta-gsj
docs/system: Add Nuvoton machine documentation
hw/arm/npcm7xx: add board setup stub for CPU and UART clocks
hw/arm: Wire up BMC boot flash for npcm750-evb and quanta-gsj
hw/ssi: NPCM7xx Flash Interface Unit device model
hw/mem: Stubbed out NPCM7xx Memory Controller model
hw/nvram: NPCM7xx OTP device model
hw/arm: Load -bios image as a boot ROM for npcm7xx
roms: Add virtual Boot ROM for NPCM7xx SoCs
hw/arm: Add two NPCM7xx-based machines
hw/arm: Add NPCM730 and NPCM750 SoC models
hw/timer: Add NPCM7xx Timer device model
hw/misc: Add NPCM7xx Clock Controller device model
hw/misc: Add NPCM7xx System Global Control Registers device model
hw/arm: versal-virt: Correct the tx/rx GEM clocks
target/arm: Count PMU events when MDCR.SPME is set
Deprecate lm32 port
Deprecate Unicore32 port
docs/system/arm/mps2.rst: Make board list consistent
hw/arm/mps2: New board model mps2-an500
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/misc/trace-events')
| -rw-r--r-- | hw/misc/trace-events | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/hw/misc/trace-events b/hw/misc/trace-events index 56a622d1e9..6054f9adf3 100644 --- a/hw/misc/trace-events +++ b/hw/misc/trace-events @@ -110,6 +110,14 @@ mos6522_set_sr_int(void) "set sr_int" mos6522_write(uint64_t addr, uint64_t val) "reg=0x%"PRIx64 " val=0x%"PRIx64 mos6522_read(uint64_t addr, unsigned val) "reg=0x%"PRIx64 " val=0x%x" +# npcm7xx_clk.c +npcm7xx_clk_read(uint64_t offset, uint32_t value) " offset: 0x%04" PRIx64 " value: 0x%08" PRIx32 +npcm7xx_clk_write(uint64_t offset, uint32_t value) "offset: 0x%04" PRIx64 " value: 0x%08" PRIx32 + +# npcm7xx_gcr.c +npcm7xx_gcr_read(uint64_t offset, uint32_t value) " offset: 0x%04" PRIx64 " value: 0x%08" PRIx32 +npcm7xx_gcr_write(uint64_t offset, uint32_t value) "offset: 0x%04" PRIx64 " value: 0x%08" PRIx32 + # stm32f4xx_syscfg.c stm32f4xx_syscfg_set_irq(int gpio, int line, int level) "Interupt: GPIO: %d, Line: %d; Level: %d" stm32f4xx_pulse_exti(int irq) "Pulse EXTI: %d" |