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| author | Peter Maydell | 2018-08-16 15:35:50 +0200 |
|---|---|---|
| committer | Peter Maydell | 2018-08-16 15:35:50 +0200 |
| commit | bb16c0412a572c2c9cd44496deb3ad430bc49c1a (patch) | |
| tree | cb87c31c5440a9128cf7762407237b5b57fbed33 /hw/misc/trace-events | |
| parent | Merge remote-tracking branch 'remotes/armbru/tags/pull-tests-2018-08-16' into... (diff) | |
| parent | hw/arm/mps2-tz: Replace init_sysbus_child() with sysbus_init_child_obj() (diff) | |
| download | qemu-bb16c0412a572c2c9cd44496deb3ad430bc49c1a.tar.gz qemu-bb16c0412a572c2c9cd44496deb3ad430bc49c1a.tar.xz qemu-bb16c0412a572c2c9cd44496deb3ad430bc49c1a.zip | |
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20180816' into staging
target-arm queue:
* Fixes for various bugs in SVE instructions
* Add model of Freescale i.MX6 UltraLite 14x14 EVK Board
* hw/arm: make bitbanded IO optional on ARMv7-M
* Add model of Cortex-M0 CPU
* Add support for loading Intel HEX files to the generic loader
* imx_spi: Unset XCH when TX FIFO becomes empty
* aspeed_sdmc: fix various bugs
* Fix bugs in Arm FP16 instruction support
* Fix aa64 FCADD and FCMLA decode
* softfloat: Fix missing inexact for floating-point add
* hw/arm/mps2-tz: Replace init_sysbus_child() with sysbus_init_child_obj()
# gpg: Signature made Thu 16 Aug 2018 14:33:41 BST
# gpg: using RSA key 3C2525ED14360CDE
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>"
# gpg: aka "Peter Maydell <pmaydell@gmail.com>"
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* remotes/pmaydell/tags/pull-target-arm-20180816: (30 commits)
hw/arm/mps2-tz: Replace init_sysbus_child() with sysbus_init_child_obj()
softfloat: Fix missing inexact for floating-point add
target/arm: Fix aa64 FCADD and FCMLA decode
target/arm: Use FZ not FZ16 for SVE FCVT single-half and double-half
target/arm: Use fp_status_fp16 for do_fmpa_zpzzz_h
target/arm: Ignore float_flag_input_denormal from fp_status_f16
target/arm: Adjust FPCR_MASK for FZ16
aspeed: add a max_ram_size property to the memory controller
aspeed_sdmc: Handle ECC training
aspeed_sdmc: Init status always idle
aspeed_sdmc: Set 'cache initial sequence' always true
aspeed_sdmc: Fix saved values
aspeed_sdmc: Extend number of valid registers
imx_spi: Unset XCH when TX FIFO becomes empty
Add QTest testcase for the Intel Hexadecimal
loader: Implement .hex file loader
loader: add rom transaction API
loader: extract rom_free() function
target/arm: add "cortex-m0" CPU model
hw/arm: make bitbanded IO optional on ARMv7-M
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/misc/trace-events')
| -rw-r--r-- | hw/misc/trace-events | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/hw/misc/trace-events b/hw/misc/trace-events index c956e1419b..1341508b33 100644 --- a/hw/misc/trace-events +++ b/hw/misc/trace-events @@ -109,3 +109,10 @@ iotkit_secctl_s_write(uint32_t offset, uint64_t data, unsigned size) "IoTKit Sec iotkit_secctl_ns_read(uint32_t offset, uint64_t data, unsigned size) "IoTKit SecCtl NS regs read: offset 0x%x data 0x%" PRIx64 " size %u" iotkit_secctl_ns_write(uint32_t offset, uint64_t data, unsigned size) "IoTKit SecCtl NS regs write: offset 0x%x data 0x%" PRIx64 " size %u" iotkit_secctl_reset(void) "IoTKit SecCtl: reset" + +# hw/misc/imx6ul_ccm.c +ccm_entry(void) "\n" +ccm_freq(uint32_t freq) "freq = %d\n" +ccm_clock_freq(uint32_t clock, uint32_t freq) "(Clock = %d) = %d\n" +ccm_read_reg(const char *reg_name, uint32_t value) "reg[%s] <= 0x%" PRIx32 "\n" +ccm_write_reg(const char *reg_name, uint32_t value) "reg[%s] => 0x%" PRIx32 "\n" |