diff options
| author | Mark Cave-Ayland | 2022-03-05 16:09:52 +0100 |
|---|---|---|
| committer | Mark Cave-Ayland | 2022-03-09 10:28:28 +0100 |
| commit | 6c7266987297cf12e1474c2d634575194096e3c8 (patch) | |
| tree | 199078891b57a4c56ac4a7a5d5990833875a9868 /hw/misc | |
| parent | mos6522: use device_class_set_parent_reset() to propagate reset to parent (diff) | |
| download | qemu-6c7266987297cf12e1474c2d634575194096e3c8.tar.gz qemu-6c7266987297cf12e1474c2d634575194096e3c8.tar.xz qemu-6c7266987297cf12e1474c2d634575194096e3c8.zip | |
mos6522: add register names to register read/write trace events
This helps to follow how the guest is programming the mos6522 when debugging.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Laurent Vivier <laurent@vivier.eu>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20220305150957.5053-8-mark.cave-ayland@ilande.co.uk>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Diffstat (limited to 'hw/misc')
| -rw-r--r-- | hw/misc/mos6522.c | 13 | ||||
| -rw-r--r-- | hw/misc/trace-events | 4 |
2 files changed, 12 insertions, 5 deletions
diff --git a/hw/misc/mos6522.c b/hw/misc/mos6522.c index 093cc83dcf..9c8d4ca6ad 100644 --- a/hw/misc/mos6522.c +++ b/hw/misc/mos6522.c @@ -36,6 +36,12 @@ #include "qemu/module.h" #include "trace.h" + +static const char *mos6522_reg_names[MOS6522_NUM_REGS] = { + "ORB", "ORA", "DDRB", "DDRA", "T1CL", "T1CH", "T1LL", "T1LH", + "T2CL", "T2CH", "SR", "ACR", "PCR", "IFR", "IER", "ANH" +}; + /* XXX: implement all timer modes */ static void mos6522_timer1_update(MOS6522State *s, MOS6522Timer *ti, @@ -310,7 +316,7 @@ uint64_t mos6522_read(void *opaque, hwaddr addr, unsigned size) } if (addr != VIA_REG_IFR || val != 0) { - trace_mos6522_read(addr, val); + trace_mos6522_read(addr, mos6522_reg_names[addr], val); } return val; @@ -321,7 +327,7 @@ void mos6522_write(void *opaque, hwaddr addr, uint64_t val, unsigned size) MOS6522State *s = opaque; MOS6522DeviceClass *mdc = MOS6522_GET_CLASS(s); - trace_mos6522_write(addr, val); + trace_mos6522_write(addr, mos6522_reg_names[addr], val); switch (addr) { case VIA_REG_B: @@ -484,7 +490,8 @@ static void mos6522_init(Object *obj) MOS6522State *s = MOS6522(obj); int i; - memory_region_init_io(&s->mem, obj, &mos6522_ops, s, "mos6522", 0x10); + memory_region_init_io(&s->mem, obj, &mos6522_ops, s, "mos6522", + MOS6522_NUM_REGS); sysbus_init_mmio(sbd, &s->mem); sysbus_init_irq(sbd, &s->irq); diff --git a/hw/misc/trace-events b/hw/misc/trace-events index fb5a389780..bd52cfc110 100644 --- a/hw/misc/trace-events +++ b/hw/misc/trace-events @@ -95,8 +95,8 @@ imx7_gpr_write(uint64_t offset, uint64_t value) "addr 0x%08" PRIx64 "value 0x%08 mos6522_set_counter(int index, unsigned int val) "T%d.counter=%d" mos6522_get_next_irq_time(uint16_t latch, int64_t d, int64_t delta) "latch=%d counter=0x%"PRId64 " delta_next=0x%"PRId64 mos6522_set_sr_int(void) "set sr_int" -mos6522_write(uint64_t addr, uint64_t val) "reg=0x%"PRIx64 " val=0x%"PRIx64 -mos6522_read(uint64_t addr, unsigned val) "reg=0x%"PRIx64 " val=0x%x" +mos6522_write(uint64_t addr, const char *name, uint64_t val) "reg=0x%"PRIx64 " [%s] val=0x%"PRIx64 +mos6522_read(uint64_t addr, const char *name, unsigned val) "reg=0x%"PRIx64 " [%s] val=0x%x" # npcm7xx_clk.c npcm7xx_clk_read(uint64_t offset, uint32_t value) " offset: 0x%04" PRIx64 " value: 0x%08" PRIx32 |