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| author | Philippe Mathieu-Daudé | 2020-09-10 09:01:27 +0200 |
|---|---|---|
| committer | Paolo Bonzini | 2020-12-10 18:15:04 +0100 |
| commit | cfbef3f4eb3816099bf573bdb238e4aad8803c4c (patch) | |
| tree | 635918f9ab427863552143dac849cc3ac691df0b /hw/net | |
| parent | hw/ssi: Rename SSI 'slave' as 'peripheral' (diff) | |
| download | qemu-cfbef3f4eb3816099bf573bdb238e4aad8803c4c.tar.gz qemu-cfbef3f4eb3816099bf573bdb238e4aad8803c4c.tar.xz qemu-cfbef3f4eb3816099bf573bdb238e4aad8803c4c.zip | |
hw/core/stream: Rename StreamSlave as StreamSink
In order to use inclusive terminology, rename 'slave stream'
as 'sink stream'.
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Acked-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-Id: <20200910070131.435543-3-philmd@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'hw/net')
| -rw-r--r-- | hw/net/xilinx_axienet.c | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/hw/net/xilinx_axienet.c b/hw/net/xilinx_axienet.c index f8cf5290e1..9bccbe9be3 100644 --- a/hw/net/xilinx_axienet.c +++ b/hw/net/xilinx_axienet.c @@ -320,8 +320,8 @@ struct XilinxAXIEnet { SysBusDevice busdev; MemoryRegion iomem; qemu_irq irq; - StreamSlave *tx_data_dev; - StreamSlave *tx_control_dev; + StreamSink *tx_data_dev; + StreamSink *tx_control_dev; XilinxAXIEnetStreamSlave rx_data_dev; XilinxAXIEnetStreamSlave rx_control_dev; NICState *nic; @@ -852,7 +852,7 @@ static ssize_t eth_rx(NetClientState *nc, const uint8_t *buf, size_t size) } static size_t -xilinx_axienet_control_stream_push(StreamSlave *obj, uint8_t *buf, size_t len, +xilinx_axienet_control_stream_push(StreamSink *obj, uint8_t *buf, size_t len, bool eop) { int i; @@ -874,7 +874,7 @@ xilinx_axienet_control_stream_push(StreamSlave *obj, uint8_t *buf, size_t len, } static size_t -xilinx_axienet_data_stream_push(StreamSlave *obj, uint8_t *buf, size_t size, +xilinx_axienet_data_stream_push(StreamSink *obj, uint8_t *buf, size_t size, bool eop) { XilinxAXIEnetStreamSlave *ds = XILINX_AXI_ENET_DATA_STREAM(obj); @@ -1002,9 +1002,9 @@ static Property xilinx_enet_properties[] = { DEFINE_PROP_UINT32("txmem", XilinxAXIEnet, c_txmem, 0x1000), DEFINE_NIC_PROPERTIES(XilinxAXIEnet, conf), DEFINE_PROP_LINK("axistream-connected", XilinxAXIEnet, - tx_data_dev, TYPE_STREAM_SLAVE, StreamSlave *), + tx_data_dev, TYPE_STREAM_SINK, StreamSink *), DEFINE_PROP_LINK("axistream-control-connected", XilinxAXIEnet, - tx_control_dev, TYPE_STREAM_SLAVE, StreamSlave *), + tx_control_dev, TYPE_STREAM_SINK, StreamSink *), DEFINE_PROP_END_OF_LIST(), }; @@ -1020,14 +1020,14 @@ static void xilinx_enet_class_init(ObjectClass *klass, void *data) static void xilinx_enet_control_stream_class_init(ObjectClass *klass, void *data) { - StreamSlaveClass *ssc = STREAM_SLAVE_CLASS(klass); + StreamSinkClass *ssc = STREAM_SINK_CLASS(klass); ssc->push = xilinx_axienet_control_stream_push; } static void xilinx_enet_data_stream_class_init(ObjectClass *klass, void *data) { - StreamSlaveClass *ssc = STREAM_SLAVE_CLASS(klass); + StreamSinkClass *ssc = STREAM_SINK_CLASS(klass); ssc->push = xilinx_axienet_data_stream_push; } @@ -1046,7 +1046,7 @@ static const TypeInfo xilinx_enet_data_stream_info = { .instance_size = sizeof(XilinxAXIEnetStreamSlave), .class_init = xilinx_enet_data_stream_class_init, .interfaces = (InterfaceInfo[]) { - { TYPE_STREAM_SLAVE }, + { TYPE_STREAM_SINK }, { } } }; @@ -1057,7 +1057,7 @@ static const TypeInfo xilinx_enet_control_stream_info = { .instance_size = sizeof(XilinxAXIEnetStreamSlave), .class_init = xilinx_enet_control_stream_class_init, .interfaces = (InterfaceInfo[]) { - { TYPE_STREAM_SLAVE }, + { TYPE_STREAM_SINK }, { } } }; |