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authorbalrog2007-07-31 03:45:35 +0200
committerbalrog2007-07-31 03:45:35 +0200
commitb30bb3a2e8ebb138494eca055bab75a4ac9c0a26 (patch)
tree57635dec914f69e00c02446a80f6717c4a4f6c84 /hw/omap.c
parentOMAP DMA input signals must be level-triggered. (diff)
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Add OMAP MMC/SD host controller.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3097 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'hw/omap.c')
-rw-r--r--hw/omap.c12
1 files changed, 8 insertions, 4 deletions
diff --git a/hw/omap.c b/hw/omap.c
index d524e82cda..e56e663a15 100644
--- a/hw/omap.c
+++ b/hw/omap.c
@@ -22,25 +22,25 @@
#include "arm_pic.h"
/* Should signal the TCMI */
-static uint32_t omap_badwidth_read16(void *opaque, target_phys_addr_t addr)
+uint32_t omap_badwidth_read16(void *opaque, target_phys_addr_t addr)
{
OMAP_16B_REG(addr);
return 0;
}
-static void omap_badwidth_write16(void *opaque, target_phys_addr_t addr,
+void omap_badwidth_write16(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
OMAP_16B_REG(addr);
}
-static uint32_t omap_badwidth_read32(void *opaque, target_phys_addr_t addr)
+uint32_t omap_badwidth_read32(void *opaque, target_phys_addr_t addr)
{
OMAP_32B_REG(addr);
return 0;
}
-static void omap_badwidth_write32(void *opaque, target_phys_addr_t addr,
+void omap_badwidth_write32(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
OMAP_32B_REG(addr);
@@ -2816,6 +2816,7 @@ static void omap_mpu_reset(void *opaque)
omap_uart_reset(mpu->uart1);
omap_uart_reset(mpu->uart2);
omap_uart_reset(mpu->uart3);
+ omap_mmc_reset(mpu->mmc);
cpu_reset(mpu->env);
}
@@ -2921,6 +2922,9 @@ struct omap_mpu_state_s *omap310_mpu_init(unsigned long sdram_size,
omap_dpll_init(&s->dpll[1], 0xfffed000, omap_findclk(s, "dpll2"));
omap_dpll_init(&s->dpll[2], 0xfffed100, omap_findclk(s, "dpll3"));
+ s->mmc = omap_mmc_init(0xfffb7800, s->irq[1][OMAP_INT_OQN],
+ &s->drq[OMAP_DMA_MMC_TX], omap_findclk(s, "mmc_ck"));
+
qemu_register_reset(omap_mpu_reset, s);
s->wakeup = qemu_allocate_irqs(omap_mpu_wakeup, s, 1)[0];