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| author | Alexander Graf | 2013-01-04 11:21:04 +0100 |
|---|---|---|
| committer | Alexander Graf | 2013-01-07 17:37:11 +0100 |
| commit | 68c2dd70068fe82a1989d0d5b70a1ab400bde19a (patch) | |
| tree | e9be2de2931bf374beb4914b33f214d31dfec0c2 /hw/openpic.c | |
| parent | PPC: KVM: set has-idle in guest device tree (diff) | |
| download | qemu-68c2dd70068fe82a1989d0d5b70a1ab400bde19a.tar.gz qemu-68c2dd70068fe82a1989d0d5b70a1ab400bde19a.tar.xz qemu-68c2dd70068fe82a1989d0d5b70a1ab400bde19a.zip | |
PPC: Bring EPR support closer to reality
We already used to support the external proxy facility of FSL MPICs,
but only implemented it halfway correctly.
This patch adds support for
* dynamic enablement of the EPR facility
* interrupt acknowledgement only when the interrupt is delivered
This way the implementation now is closer to real hardware.
Signed-off-by: Alexander Graf <agraf@suse.de>
Diffstat (limited to 'hw/openpic.c')
| -rw-r--r-- | hw/openpic.c | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/hw/openpic.c b/hw/openpic.c index e773d680f4..3b20a39ab5 100644 --- a/hw/openpic.c +++ b/hw/openpic.c @@ -131,6 +131,9 @@ static const int debug_openpic = 0; #define VIR_GENERIC 0x00000000 /* Generic Vendor ID */ #define GCR_RESET 0x80000000 +#define GCR_MODE_PASS 0x00000000 +#define GCR_MODE_MIXED 0x20000000 +#define GCR_MODE_PROXY 0x60000000 #define TBCR_CI 0x80000000 /* count inhibit */ #define TCCR_TOG 0x80000000 /* toggles when decrement to zero */ @@ -233,6 +236,7 @@ typedef struct OpenPICState { uint32_t ivpr_reset; uint32_t idr_reset; uint32_t brr1; + uint32_t mpic_mode_mask; /* Sub-regions */ MemoryRegion sub_io_mem[5]; @@ -667,6 +671,20 @@ static void openpic_gbl_write(void *opaque, hwaddr addr, uint64_t val, case 0x1020: /* GCR */ if (val & GCR_RESET) { openpic_reset(&opp->busdev.qdev); + } else if (opp->mpic_mode_mask) { + CPUArchState *env; + int mpic_proxy = 0; + + opp->gcr &= ~opp->mpic_mode_mask; + opp->gcr |= val & opp->mpic_mode_mask; + + /* Set external proxy mode */ + if ((val & opp->mpic_mode_mask) == GCR_MODE_PROXY) { + mpic_proxy = 1; + } + for (env = first_cpu; env != NULL; env = env->next_cpu) { + env->mpic_proxy = mpic_proxy; + } } break; case 0x1080: /* VIR */ @@ -1407,6 +1425,9 @@ static int openpic_init(SysBusDevice *dev) opp->irq_tim0 = FSL_MPIC_20_TMR_IRQ; opp->irq_msi = FSL_MPIC_20_MSI_IRQ; opp->brr1 = FSL_BRR1_IPID | FSL_BRR1_IPMJ | FSL_BRR1_IPMN; + /* XXX really only available as of MPIC 4.0 */ + opp->mpic_mode_mask = GCR_MODE_PROXY; + msi_supported = true; list = list_be; |