diff options
author | Marc-André Lureau | 2020-01-10 16:30:32 +0100 |
---|---|---|
committer | Paolo Bonzini | 2020-01-24 20:59:15 +0100 |
commit | 4f67d30b5e74e060b8dbe10528829b47345cd6e8 (patch) | |
tree | 025b44a1cb86fe029ed4c105b2764a13c21c5bba /hw/pci-bridge | |
parent | object: return self in object_ref() (diff) | |
download | qemu-4f67d30b5e74e060b8dbe10528829b47345cd6e8.tar.gz qemu-4f67d30b5e74e060b8dbe10528829b47345cd6e8.tar.xz qemu-4f67d30b5e74e060b8dbe10528829b47345cd6e8.zip |
qdev: set properties with device_class_set_props()
The following patch will need to handle properties registration during
class_init time. Let's use a device_class_set_props() setter.
spatch --macro-file scripts/cocci-macro-file.h --sp-file
./scripts/coccinelle/qdev-set-props.cocci --keep-comments --in-place
--dir .
@@
typedef DeviceClass;
DeviceClass *d;
expression val;
@@
- d->props = val
+ device_class_set_props(d, val)
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Message-Id: <20200110153039.1379601-20-marcandre.lureau@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'hw/pci-bridge')
-rw-r--r-- | hw/pci-bridge/gen_pcie_root_port.c | 2 | ||||
-rw-r--r-- | hw/pci-bridge/pci_bridge_dev.c | 2 | ||||
-rw-r--r-- | hw/pci-bridge/pci_expander_bridge.c | 4 | ||||
-rw-r--r-- | hw/pci-bridge/pcie_pci_bridge.c | 2 | ||||
-rw-r--r-- | hw/pci-bridge/pcie_root_port.c | 2 | ||||
-rw-r--r-- | hw/pci-bridge/xio3130_downstream.c | 2 |
6 files changed, 7 insertions, 7 deletions
diff --git a/hw/pci-bridge/gen_pcie_root_port.c b/hw/pci-bridge/gen_pcie_root_port.c index 9eaefebca8..bb26e272c1 100644 --- a/hw/pci-bridge/gen_pcie_root_port.c +++ b/hw/pci-bridge/gen_pcie_root_port.c @@ -147,7 +147,7 @@ static void gen_rp_dev_class_init(ObjectClass *klass, void *data) k->device_id = PCI_DEVICE_ID_REDHAT_PCIE_RP; dc->desc = "PCI Express Root Port"; dc->vmsd = &vmstate_rp_dev; - dc->props = gen_rp_props; + device_class_set_props(dc, gen_rp_props); device_class_set_parent_realize(dc, gen_rp_realize, &rpc->parent_realize); diff --git a/hw/pci-bridge/pci_bridge_dev.c b/hw/pci-bridge/pci_bridge_dev.c index cc80cb4898..4a080b7c7b 100644 --- a/hw/pci-bridge/pci_bridge_dev.c +++ b/hw/pci-bridge/pci_bridge_dev.c @@ -258,7 +258,7 @@ static void pci_bridge_dev_class_init(ObjectClass *klass, void *data) k->is_bridge = true; dc->desc = "Standard PCI Bridge"; dc->reset = qdev_pci_bridge_dev_reset; - dc->props = pci_bridge_dev_properties; + device_class_set_props(dc, pci_bridge_dev_properties); dc->vmsd = &pci_bridge_dev_vmstate; set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); hc->plug = pci_bridge_dev_plug_cb; diff --git a/hw/pci-bridge/pci_expander_bridge.c b/hw/pci-bridge/pci_expander_bridge.c index 0592818447..47aaaf8fd1 100644 --- a/hw/pci-bridge/pci_expander_bridge.c +++ b/hw/pci-bridge/pci_expander_bridge.c @@ -309,7 +309,7 @@ static void pxb_dev_class_init(ObjectClass *klass, void *data) k->class_id = PCI_CLASS_BRIDGE_HOST; dc->desc = "PCI Expander Bridge"; - dc->props = pxb_dev_properties; + device_class_set_props(dc, pxb_dev_properties); dc->hotpluggable = false; set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); } @@ -347,7 +347,7 @@ static void pxb_pcie_dev_class_init(ObjectClass *klass, void *data) k->class_id = PCI_CLASS_BRIDGE_HOST; dc->desc = "PCI Express Expander Bridge"; - dc->props = pxb_dev_properties; + device_class_set_props(dc, pxb_dev_properties); dc->hotpluggable = false; set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); } diff --git a/hw/pci-bridge/pcie_pci_bridge.c b/hw/pci-bridge/pcie_pci_bridge.c index 7679bef6c1..eade133968 100644 --- a/hw/pci-bridge/pcie_pci_bridge.c +++ b/hw/pci-bridge/pcie_pci_bridge.c @@ -152,7 +152,7 @@ static void pcie_pci_bridge_class_init(ObjectClass *klass, void *data) k->exit = pcie_pci_bridge_exit; k->config_write = pcie_pci_bridge_write_config; dc->vmsd = &pcie_pci_bridge_dev_vmstate; - dc->props = pcie_pci_bridge_dev_properties; + device_class_set_props(dc, pcie_pci_bridge_dev_properties); dc->reset = &pcie_pci_bridge_reset; set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); hc->plug = pci_bridge_dev_plug_cb; diff --git a/hw/pci-bridge/pcie_root_port.c b/hw/pci-bridge/pcie_root_port.c index 012c2cb12c..0ba4e4dea4 100644 --- a/hw/pci-bridge/pcie_root_port.c +++ b/hw/pci-bridge/pcie_root_port.c @@ -174,7 +174,7 @@ static void rp_class_init(ObjectClass *klass, void *data) k->exit = rp_exit; set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); dc->reset = rp_reset; - dc->props = rp_props; + device_class_set_props(dc, rp_props); } static const TypeInfo rp_info = { diff --git a/hw/pci-bridge/xio3130_downstream.c b/hw/pci-bridge/xio3130_downstream.c index a9f084b863..153a4acad2 100644 --- a/hw/pci-bridge/xio3130_downstream.c +++ b/hw/pci-bridge/xio3130_downstream.c @@ -169,7 +169,7 @@ static void xio3130_downstream_class_init(ObjectClass *klass, void *data) dc->desc = "TI X3130 Downstream Port of PCI Express Switch"; dc->reset = xio3130_downstream_reset; dc->vmsd = &vmstate_xio3130_downstream; - dc->props = xio3130_downstream_props; + device_class_set_props(dc, xio3130_downstream_props); } static const TypeInfo xio3130_downstream_info = { |