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authorMarkus Armbruster2016-06-15 19:56:31 +0200
committerMichael S. Tsirkin2016-07-04 13:52:10 +0200
commit01c9742d9d5a48c55a0155875657944c2159762c (patch)
tree91bcffa48078f7173510f32b9f78faca89a945cf /hw/pci-host/q35.c
parentpiix: Set I440FXState member pci_info.w32 in one place (diff)
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pc: Eliminate PcPciInfo
PcPciInfo has two (ill-named) members: Range w32 is the PCI hole, and w64 is the PCI64 hole. Three users: * I440FXState and MCHPCIState have a member PcPciInfo pci_info, but only pci_info.w32 is actually used. This is confusing. Replace by Range pci_hole. * acpi_build() uses auto PcPciInfo pci_info to forward both PCI holes from acpi_get_pci_info() to build_dsdt(). Replace by two variables Range pci_hole, pci_hole64. Rename acpi_get_pci_info() to acpi_get_pci_holes(). PcPciInfo is now unused; drop it. Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Reviewed-by: Marcel Apfelbaum <marcel@redhat.com>
Diffstat (limited to 'hw/pci-host/q35.c')
-rw-r--r--hw/pci-host/q35.c12
1 files changed, 6 insertions, 6 deletions
diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c
index eb1b2f77b7..f908ba36be 100644
--- a/hw/pci-host/q35.c
+++ b/hw/pci-host/q35.c
@@ -74,7 +74,7 @@ static void q35_host_get_pci_hole_start(Object *obj, Visitor *v,
Error **errp)
{
Q35PCIHost *s = Q35_HOST_DEVICE(obj);
- uint32_t value = s->mch.pci_info.w32.begin;
+ uint32_t value = s->mch.pci_hole.begin;
visit_type_uint32(v, name, &value, errp);
}
@@ -84,7 +84,7 @@ static void q35_host_get_pci_hole_end(Object *obj, Visitor *v,
Error **errp)
{
Q35PCIHost *s = Q35_HOST_DEVICE(obj);
- uint32_t value = s->mch.pci_info.w32.end;
+ uint32_t value = s->mch.pci_hole.end;
visit_type_uint32(v, name, &value, errp);
}
@@ -205,9 +205,9 @@ static void q35_host_initfn(Object *obj)
* it's not a power of two, which means an MTRR
* can't cover it exactly.
*/
- s->mch.pci_info.w32.begin = MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT +
+ s->mch.pci_hole.begin = MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT +
MCH_HOST_BRIDGE_PCIEXBAR_MAX;
- s->mch.pci_info.w32.end = IO_APIC_DEFAULT_ADDRESS;
+ s->mch.pci_hole.end = IO_APIC_DEFAULT_ADDRESS;
}
static const TypeInfo q35_host_info = {
@@ -288,9 +288,9 @@ static void mch_update_pciexbar(MCHPCIState *mch)
* which means an MTRR can't cover it exactly.
*/
if (enable) {
- mch->pci_info.w32.begin = addr + length;
+ mch->pci_hole.begin = addr + length;
} else {
- mch->pci_info.w32.begin = MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT;
+ mch->pci_hole.begin = MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT;
}
}