diff options
| author | Peter Maydell | 2017-03-16 12:05:47 +0100 |
|---|---|---|
| committer | Peter Maydell | 2017-03-16 12:05:47 +0100 |
| commit | 3716fba3f58de0eea32b8da29976c902549cc836 (patch) | |
| tree | ed8a5bcc724035d18419f2c8b5f23ba49cb4de7f /hw/pci/pcie.c | |
| parent | Merge remote-tracking branch 'remotes/jnsnow/tags/ide-pull-request' into staging (diff) | |
| parent | virtio-serial-bus: Delete timer from list before free it (diff) | |
| download | qemu-3716fba3f58de0eea32b8da29976c902549cc836.tar.gz qemu-3716fba3f58de0eea32b8da29976c902549cc836.tar.xz qemu-3716fba3f58de0eea32b8da29976c902549cc836.zip | |
Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging
virtio, pci: fixes
More fixes missed in the previous pull request.
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
# gpg: Signature made Thu 16 Mar 2017 02:29:49 GMT
# gpg: using RSA key 0x281F0DB8D28D5469
# gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>"
# gpg: aka "Michael S. Tsirkin <mst@redhat.com>"
# Primary key fingerprint: 0270 606B 6F3C DF3D 0B17 0970 C350 3912 AFBE 8E67
# Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA 8A0D 281F 0DB8 D28D 5469
* remotes/mst/tags/for_upstream:
virtio-serial-bus: Delete timer from list before free it
hw/virtio: fix Power Management Control Register for PCI Express virtio devices
hw/virtio: fix Link Control Register for PCI Express virtio devices
hw/virtio: fix error enabling flags in Device Control register
hw/pcie: fix Extended Configuration Space for devices with no Extended Capabilities
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/pci/pcie.c')
| -rw-r--r-- | hw/pci/pcie.c | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/hw/pci/pcie.c b/hw/pci/pcie.c index fc54bfd53d..18e634f577 100644 --- a/hw/pci/pcie.c +++ b/hw/pci/pcie.c @@ -109,6 +109,12 @@ int pcie_cap_init(PCIDevice *dev, uint8_t offset, uint8_t type, uint8_t port) PCI_EXP_DEVCAP2_EFF | PCI_EXP_DEVCAP2_EETLPP); pci_set_word(dev->wmask + pos + PCI_EXP_DEVCTL2, PCI_EXP_DEVCTL2_EETLPPB); + + if (dev->cap_present & QEMU_PCIE_EXTCAP_INIT) { + /* read-only to behave like a 'NULL' Extended Capability Header */ + pci_set_long(dev->wmask + PCI_CONFIG_SPACE_SIZE, 0); + } + return pos; } @@ -217,6 +223,20 @@ void pcie_cap_deverr_reset(PCIDevice *dev) PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE); } +void pcie_cap_lnkctl_init(PCIDevice *dev) +{ + uint32_t pos = dev->exp.exp_cap; + pci_long_test_and_set_mask(dev->wmask + pos + PCI_EXP_LNKCTL, + PCI_EXP_LNKCTL_CCC | PCI_EXP_LNKCTL_ES); +} + +void pcie_cap_lnkctl_reset(PCIDevice *dev) +{ + uint8_t *lnkctl = dev->config + dev->exp.exp_cap + PCI_EXP_LNKCTL; + pci_long_test_and_clear_mask(lnkctl, + PCI_EXP_LNKCTL_CCC | PCI_EXP_LNKCTL_ES); +} + static void hotplug_event_update_event_status(PCIDevice *dev) { uint32_t pos = dev->exp.exp_cap; |