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| author | Ben Widawsky | 2022-04-29 16:40:41 +0200 |
|---|---|---|
| committer | Michael S. Tsirkin | 2022-05-13 12:13:36 +0200 |
| commit | d86d30192b7bc5a10fa6c82c073f55aea25f9291 (patch) | |
| tree | 4c7c65ccabf4eda78e0f323636edbe30243746b8 /hw/pci | |
| parent | qtest/cxl: Introduce initial test for pxb-cxl only. (diff) | |
| download | qemu-d86d30192b7bc5a10fa6c82c073f55aea25f9291.tar.gz qemu-d86d30192b7bc5a10fa6c82c073f55aea25f9291.tar.xz qemu-d86d30192b7bc5a10fa6c82c073f55aea25f9291.zip | |
hw/cxl/rp: Add a root port
This adds just enough of a root port implementation to be able to
enumerate root ports (creating the required DVSEC entries). What's not
here yet is the MMIO nor the ability to write some of the DVSEC entries.
This can be added with the qemu commandline by adding a rootport to a
specific CXL host bridge. For example:
-device cxl-rp,id=rp0,bus="cxl.0",addr=0.0,chassis=4
Like the host bridge patch, the ACPI tables aren't generated at this
point and so system software cannot use it.
Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20220429144110.25167-17-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Diffstat (limited to 'hw/pci')
| -rw-r--r-- | hw/pci/pci.c | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/hw/pci/pci.c b/hw/pci/pci.c index 6c0656f604..a9b37f8000 100644 --- a/hw/pci/pci.c +++ b/hw/pci/pci.c @@ -2762,7 +2762,9 @@ static void pci_device_class_base_init(ObjectClass *klass, void *data) object_class_dynamic_cast(klass, INTERFACE_CONVENTIONAL_PCI_DEVICE); ObjectClass *pcie = object_class_dynamic_cast(klass, INTERFACE_PCIE_DEVICE); - assert(conventional || pcie); + ObjectClass *cxl = + object_class_dynamic_cast(klass, INTERFACE_CXL_DEVICE); + assert(conventional || pcie || cxl); } } |