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authorCédric Le Goater2019-10-07 10:40:55 +0200
committerDavid Gibson2019-10-24 00:36:55 +0200
commit06d26eeb47de96c0fa0cc1d5e95124b0a809b3ac (patch)
treeb682e161a498eccb0ac24f55f7d3f4651f89ac74 /hw/ppc/pnv_psi.c
parentppc/pnv: Improve trigger data definition (diff)
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ppc/pnv: Use address_space_stq_be() when triggering an interrupt from PSI
Include the XIVE_TRIGGER_PQ bit in the trigger data which is how hardware signals to the IC that the PQ bits of the interrupt source have been checked. Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20191007084102.29776-3-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Diffstat (limited to 'hw/ppc/pnv_psi.c')
-rw-r--r--hw/ppc/pnv_psi.c15
1 files changed, 12 insertions, 3 deletions
diff --git a/hw/ppc/pnv_psi.c b/hw/ppc/pnv_psi.c
index a997f16bb4..68d0dfacfe 100644
--- a/hw/ppc/pnv_psi.c
+++ b/hw/ppc/pnv_psi.c
@@ -660,10 +660,19 @@ static void pnv_psi_notify(XiveNotifier *xf, uint32_t srcno)
uint32_t offset =
(psi->regs[PSIHB_REG(PSIHB9_IVT_OFFSET)] >> PSIHB9_IVT_OFF_SHIFT);
- uint64_t lisn = cpu_to_be64(offset + srcno);
+ uint64_t data = XIVE_TRIGGER_PQ | offset | srcno;
+ MemTxResult result;
- if (valid) {
- cpu_physical_memory_write(notify_addr, &lisn, sizeof(lisn));
+ if (!valid) {
+ return;
+ }
+
+ address_space_stq_be(&address_space_memory, notify_addr, data,
+ MEMTXATTRS_UNSPECIFIED, &result);
+ if (result != MEMTX_OK) {
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: trigger failed @%"
+ HWADDR_PRIx "\n", __func__, notif_port);
+ return;
}
}