diff options
| author | Cédric Le Goater | 2019-12-05 19:44:51 +0100 |
|---|---|---|
| committer | David Gibson | 2019-12-17 00:39:48 +0100 |
| commit | 2b548a4255ca07cf4d467b7fb3bdf2ab79b7dff5 (patch) | |
| tree | cfb8f185a3887bb832f734af3a903c514491fd63 /hw/ppc/pnv_xscom.c | |
| parent | target/ppc: Add POWER10 DD1.0 model information (diff) | |
| download | qemu-2b548a4255ca07cf4d467b7fb3bdf2ab79b7dff5.tar.gz qemu-2b548a4255ca07cf4d467b7fb3bdf2ab79b7dff5.tar.xz qemu-2b548a4255ca07cf4d467b7fb3bdf2ab79b7dff5.zip | |
ppc/pnv: Introduce a POWER10 PnvChip and a powernv10 machine
This is an empty shell with the XSCOM bus and cores. The chip controllers
will come later.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20191205184454.10722-3-clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Diffstat (limited to 'hw/ppc/pnv_xscom.c')
| -rw-r--r-- | hw/ppc/pnv_xscom.c | 23 |
1 files changed, 18 insertions, 5 deletions
diff --git a/hw/ppc/pnv_xscom.c b/hw/ppc/pnv_xscom.c index f01d788a65..b3d3b6e350 100644 --- a/hw/ppc/pnv_xscom.c +++ b/hw/ppc/pnv_xscom.c @@ -69,10 +69,16 @@ static uint32_t pnv_xscom_pcba(PnvChip *chip, uint64_t addr) { addr &= (PNV_XSCOM_SIZE - 1); - if (pnv_chip_is_power9(chip)) { - return addr >> 3; - } else { + switch (PNV_CHIP_GET_CLASS(chip)->chip_type) { + case PNV_CHIP_POWER8E: + case PNV_CHIP_POWER8: + case PNV_CHIP_POWER8NVL: return ((addr >> 4) & ~0xfull) | ((addr >> 3) & 0xf); + case PNV_CHIP_POWER9: + case PNV_CHIP_POWER10: + return addr >> 3; + default: + g_assert_not_reached(); } } @@ -307,6 +313,7 @@ static int xscom_dt_child(Object *child, void *opaque) static const char compat_p8[] = "ibm,power8-xscom\0ibm,xscom"; static const char compat_p9[] = "ibm,power9-xscom\0ibm,xscom"; +static const char compat_p10[] = "ibm,power10-xscom\0ibm,xscom"; int pnv_dt_xscom(PnvChip *chip, void *fdt, int root_offset) { @@ -315,7 +322,10 @@ int pnv_dt_xscom(PnvChip *chip, void *fdt, int root_offset) ForeachPopulateArgs args; char *name; - if (pnv_chip_is_power9(chip)) { + if (pnv_chip_is_power10(chip)) { + reg[0] = cpu_to_be64(PNV10_XSCOM_BASE(chip)); + reg[1] = cpu_to_be64(PNV10_XSCOM_SIZE); + } else if (pnv_chip_is_power9(chip)) { reg[0] = cpu_to_be64(PNV9_XSCOM_BASE(chip)); reg[1] = cpu_to_be64(PNV9_XSCOM_SIZE); } else { @@ -332,7 +342,10 @@ int pnv_dt_xscom(PnvChip *chip, void *fdt, int root_offset) _FDT((fdt_setprop_cell(fdt, xscom_offset, "#size-cells", 1))); _FDT((fdt_setprop(fdt, xscom_offset, "reg", reg, sizeof(reg)))); - if (pnv_chip_is_power9(chip)) { + if (pnv_chip_is_power10(chip)) { + _FDT((fdt_setprop(fdt, xscom_offset, "compatible", compat_p10, + sizeof(compat_p10)))); + } else if (pnv_chip_is_power9(chip)) { _FDT((fdt_setprop(fdt, xscom_offset, "compatible", compat_p9, sizeof(compat_p9)))); } else { |