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| author | Suraj Jitindar Singh | 2019-11-28 14:46:57 +0100 |
|---|---|---|
| committer | David Gibson | 2019-12-17 00:39:48 +0100 |
| commit | f0ec31b1e21718b728753bcbfad54862a587050f (patch) | |
| tree | 86855c0dd678f32de9264905b86246ffc7a38087 /hw/ppc/ppc.c | |
| parent | target/ppc: Add SPR ASDR (diff) | |
| download | qemu-f0ec31b1e21718b728753bcbfad54862a587050f.tar.gz qemu-f0ec31b1e21718b728753bcbfad54862a587050f.tar.xz qemu-f0ec31b1e21718b728753bcbfad54862a587050f.zip | |
target/ppc: Add SPR TBU40
The spr TBU40 is used to set the upper 40 bits of the timebase
register, present on POWER5+ and later processors.
This register can only be written by the hypervisor, and cannot be read.
Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20191128134700.16091-5-clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Diffstat (limited to 'hw/ppc/ppc.c')
| -rw-r--r-- | hw/ppc/ppc.c | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/hw/ppc/ppc.c b/hw/ppc/ppc.c index 2856d69495..4c5fa29399 100644 --- a/hw/ppc/ppc.c +++ b/hw/ppc/ppc.c @@ -698,6 +698,19 @@ void cpu_ppc_store_vtb(CPUPPCState *env, uint64_t value) &tb_env->vtb_offset, value); } +void cpu_ppc_store_tbu40(CPUPPCState *env, uint64_t value) +{ + ppc_tb_t *tb_env = env->tb_env; + uint64_t tb; + + tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), + tb_env->tb_offset); + tb &= 0xFFFFFFUL; + tb |= (value & ~0xFFFFFFUL); + cpu_ppc_store_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), + &tb_env->tb_offset, tb); +} + static void cpu_ppc_tb_stop (CPUPPCState *env) { ppc_tb_t *tb_env = env->tb_env; |