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authorDavid Gibson2019-09-25 07:12:07 +0200
committerDavid Gibson2019-10-04 11:08:23 +0200
commitca62823b79443e3f498c6e6b9fea5f8bbe61033e (patch)
tree1b2e838e044ab583a81d8b998d14feedef313a8b /hw/ppc/spapr_hcall.c
parentxive: Improve irq claim/free path (diff)
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spapr: Use less cryptic representation of which irq backends are supported
SpaprIrq::ov5 stores the value for a particular byte in PAPR option vector 5 which indicates whether XICS, XIVE or both interrupt controllers are available. As usual for PAPR, the encoding is kind of overly complicated and confusing (though to be fair there are some backwards compat things it has to handle). But to make our internal code clearer, have SpaprIrq encode more directly which backends are available as two booleans, and derive the OV5 value from that at the point we need it. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Greg Kurz <groug@kaod.org>
Diffstat (limited to 'hw/ppc/spapr_hcall.c')
-rw-r--r--hw/ppc/spapr_hcall.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c
index 3d3a67149a..140f05c1c6 100644
--- a/hw/ppc/spapr_hcall.c
+++ b/hw/ppc/spapr_hcall.c
@@ -1784,13 +1784,13 @@ static target_ulong h_client_architecture_support(PowerPCCPU *cpu,
* terminate the boot.
*/
if (guest_xive) {
- if (spapr->irq->ov5 == SPAPR_OV5_XIVE_LEGACY) {
+ if (!spapr->irq->xive) {
error_report(
"Guest requested unavailable interrupt mode (XIVE), try the ic-mode=xive or ic-mode=dual machine property");
exit(EXIT_FAILURE);
}
} else {
- if (spapr->irq->ov5 == SPAPR_OV5_XIVE_EXPLOIT) {
+ if (!spapr->irq->xics) {
error_report(
"Guest requested unavailable interrupt mode (XICS), either don't set the ic-mode machine property or try ic-mode=xics or ic-mode=dual");
exit(EXIT_FAILURE);
@@ -1804,7 +1804,7 @@ static target_ulong h_client_architecture_support(PowerPCCPU *cpu,
*/
if (!spapr->cas_reboot) {
spapr->cas_reboot = spapr_ovec_test(ov5_updates, OV5_XIVE_EXPLOIT)
- && spapr->irq->ov5 & SPAPR_OV5_XIVE_BOTH;
+ && spapr->irq->xics && spapr->irq->xive;
}
spapr_ovec_cleanup(ov5_updates);