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| author | Andreas Färber | 2013-01-18 15:57:51 +0100 |
|---|---|---|
| committer | Andreas Färber | 2013-02-16 14:50:59 +0100 |
| commit | f3273ba643f2d0221492381b24bbc35fb6089a48 (patch) | |
| tree | b50f0b68f7071a957da30e609d5b17c37e7dda4f /hw/ppc405_uc.c | |
| parent | target-xtensa: Move TCG initialization to XtensaCPU initfn (diff) | |
| download | qemu-f3273ba643f2d0221492381b24bbc35fb6089a48.tar.gz qemu-f3273ba643f2d0221492381b24bbc35fb6089a48.tar.xz qemu-f3273ba643f2d0221492381b24bbc35fb6089a48.zip | |
ppc405_uc: Pass PowerPCCPU to ppc40x_{core,chip,system}_reset()
Prepares for changing cpu_interrupt() argument to CPUState.
Signed-off-by: Andreas Färber <afaerber@suse.de>
Acked-by: Alexander Graf <agraf@suse.de>
Diffstat (limited to 'hw/ppc405_uc.c')
| -rw-r--r-- | hw/ppc405_uc.c | 16 |
1 files changed, 10 insertions, 6 deletions
diff --git a/hw/ppc405_uc.c b/hw/ppc405_uc.c index c96d103d1c..d8cbe875bd 100644 --- a/hw/ppc405_uc.c +++ b/hw/ppc405_uc.c @@ -1770,8 +1770,9 @@ static void ppc405_mal_init(CPUPPCState *env, qemu_irq irqs[4]) /*****************************************************************************/ /* SPR */ -void ppc40x_core_reset (CPUPPCState *env) +void ppc40x_core_reset(PowerPCCPU *cpu) { + CPUPPCState *env = &cpu->env; target_ulong dbsr; printf("Reset PowerPC core\n"); @@ -1782,8 +1783,9 @@ void ppc40x_core_reset (CPUPPCState *env) env->spr[SPR_40x_DBSR] = dbsr; } -void ppc40x_chip_reset (CPUPPCState *env) +void ppc40x_chip_reset(PowerPCCPU *cpu) { + CPUPPCState *env = &cpu->env; target_ulong dbsr; printf("Reset PowerPC chip\n"); @@ -1795,7 +1797,7 @@ void ppc40x_chip_reset (CPUPPCState *env) env->spr[SPR_40x_DBSR] = dbsr; } -void ppc40x_system_reset (CPUPPCState *env) +void ppc40x_system_reset(PowerPCCPU *cpu) { printf("Reset PowerPC system\n"); qemu_system_reset_request(); @@ -1803,21 +1805,23 @@ void ppc40x_system_reset (CPUPPCState *env) void store_40x_dbcr0 (CPUPPCState *env, uint32_t val) { + PowerPCCPU *cpu = ppc_env_get_cpu(env); + switch ((val >> 28) & 0x3) { case 0x0: /* No action */ break; case 0x1: /* Core reset */ - ppc40x_core_reset(env); + ppc40x_core_reset(cpu); break; case 0x2: /* Chip reset */ - ppc40x_chip_reset(env); + ppc40x_chip_reset(cpu); break; case 0x3: /* System reset */ - ppc40x_system_reset(env); + ppc40x_system_reset(cpu); break; } } |