diff options
| author | Bin Meng | 2021-02-03 15:24:47 +0100 |
|---|---|---|
| committer | David Gibson | 2021-02-10 04:50:11 +0100 |
| commit | 0c36ab7114056caa78471016b8990f983168ff47 (patch) | |
| tree | af370944e8ff0eaba82d1eae337b4076446f23b6 /hw/ppc | |
| parent | ppc/pnv: Set default RAM size to 1 GB (diff) | |
| download | qemu-0c36ab7114056caa78471016b8990f983168ff47.tar.gz qemu-0c36ab7114056caa78471016b8990f983168ff47.tar.xz qemu-0c36ab7114056caa78471016b8990f983168ff47.zip | |
hw/ppc: e500: Use a macro for the platform clock frequency
At present the platform clock frequency is using a magic number.
Convert it to a macro and use it everywhere.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <1612362288-22216-1-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Diffstat (limited to 'hw/ppc')
| -rw-r--r-- | hw/ppc/e500.c | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c index c64b5d08bd..c795276668 100644 --- a/hw/ppc/e500.c +++ b/hw/ppc/e500.c @@ -74,6 +74,8 @@ #define MPC8544_I2C_IRQ 43 #define RTC_REGS_OFFSET 0x68 +#define PLATFORM_CLK_FREQ_HZ (400 * 1000 * 1000) + struct boot_info { uint32_t dt_base; @@ -320,8 +322,8 @@ static int ppce500_load_device_tree(PPCE500MachineState *pms, int fdt_size; void *fdt; uint8_t hypercall[16]; - uint32_t clock_freq = 400000000; - uint32_t tb_freq = 400000000; + uint32_t clock_freq = PLATFORM_CLK_FREQ_HZ; + uint32_t tb_freq = PLATFORM_CLK_FREQ_HZ; int i; char compatible_sb[] = "fsl,mpc8544-immr\0simple-bus"; char *soc; @@ -890,7 +892,7 @@ void ppce500_init(MachineState *machine) env->spr_cb[SPR_BOOKE_PIR].default_value = cs->cpu_index = i; env->mpic_iack = pmc->ccsrbar_base + MPC8544_MPIC_REGS_OFFSET + 0xa0; - ppc_booke_timers_init(cpu, 400000000, PPC_TIMER_E500); + ppc_booke_timers_init(cpu, PLATFORM_CLK_FREQ_HZ, PPC_TIMER_E500); /* Register reset handler */ if (!i) { |