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| author | Matheus Ferst | 2021-07-20 15:55:07 +0200 |
|---|---|---|
| committer | David Gibson | 2021-07-29 02:59:49 +0200 |
| commit | 2d1154bd95a8bfea30cc59de8e080e5a016a9bee (patch) | |
| tree | 05085bececbd3ad4351207fcdd1d910c31976890 /hw/ppc | |
| parent | i2c/smbus_eeprom: Add feature bit to SPD data (diff) | |
| download | qemu-2d1154bd95a8bfea30cc59de8e080e5a016a9bee.tar.gz qemu-2d1154bd95a8bfea30cc59de8e080e5a016a9bee.tar.xz qemu-2d1154bd95a8bfea30cc59de8e080e5a016a9bee.zip | |
target/ppc: Ease L=0 requirement on cmp/cmpi/cmpl/cmpli for ppc32
In commit 8f0a4b6a9b, we started to require L=0 for ppc32 to match what
The Programming Environments Manual say:
"For 32-bit implementations, the L field must be cleared, otherwise
the instruction form is invalid."
The stricter behavior, however, broke AROS boot on sam460ex, which is a
regression from 6.0. This patch partially reverts the change, raising
the exception only for CPUs known to require L=0 (e500 and e500mc) and
logging a guest error for other cases.
Both behaviors are acceptable by the PowerISA, which allows "the system
illegal instruction error handler to be invoked or yield boundedly
undefined results."
Reported-by: BALATON Zoltan <balaton@eik.bme.hu>
Fixes: 8f0a4b6a9b ("target/ppc: Move cmp/cmpi/cmpl/cmpli to decodetree")
Tested-by: BALATON Zoltan <balaton@eik.bme.hu>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20210720135507.2444635-1-matheus.ferst@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Diffstat (limited to 'hw/ppc')
0 files changed, 0 insertions, 0 deletions