diff options
| author | Cédric Le Goater | 2017-07-05 19:13:14 +0200 |
|---|---|---|
| committer | David Gibson | 2017-07-11 03:04:02 +0200 |
| commit | f2b14e3a9f2e6c6c35a90dd282ea55e8bcb61b8d (patch) | |
| tree | dc9e0b72ce5548eac72d96a8896c3e273cc0978f /hw/ppc | |
| parent | ppc/kvm: have the "family" CPU alias to point to TYPE_HOST_POWERPC_CPU (diff) | |
| download | qemu-f2b14e3a9f2e6c6c35a90dd282ea55e8bcb61b8d.tar.gz qemu-f2b14e3a9f2e6c6c35a90dd282ea55e8bcb61b8d.tar.xz qemu-f2b14e3a9f2e6c6c35a90dd282ea55e8bcb61b8d.zip | |
spapr: introduce the XIVE_EXPLOIT option in CAS
On POWER9, the Client Architecture Support (CAS) negotiation process
determines whether the guest operates in XIVE Legacy compatibility
(the former POWER8 interrupt model) or in XIVE exploitation mode (the
newer POWER9 interrupt model).
Bit 7 of Byte 23 of vector 5 is used for this purpose.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Diffstat (limited to 'hw/ppc')
| -rw-r--r-- | hw/ppc/spapr.c | 13 |
1 files changed, 7 insertions, 6 deletions
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index ba8f57a5a0..ff78a225fd 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -910,7 +910,8 @@ static void spapr_dt_ov5_platform_support(void *fdt, int chosen) { PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu); - char val[2 * 3] = { + char val[2 * 4] = { + 23, 0x00, /* Xive mode: 0 = legacy (as in ISA 2.7), 1 = Exploitation */ 24, 0x00, /* Hash/Radix, filled in below. */ 25, 0x00, /* Hash options: Segment Tables == no, GTSE == no. */ 26, 0x40, /* Radix options: GTSE == yes. */ @@ -918,19 +919,19 @@ static void spapr_dt_ov5_platform_support(void *fdt, int chosen) if (kvm_enabled()) { if (kvmppc_has_cap_mmu_radix() && kvmppc_has_cap_mmu_hash_v3()) { - val[1] = 0x80; /* OV5_MMU_BOTH */ + val[3] = 0x80; /* OV5_MMU_BOTH */ } else if (kvmppc_has_cap_mmu_radix()) { - val[1] = 0x40; /* OV5_MMU_RADIX_300 */ + val[3] = 0x40; /* OV5_MMU_RADIX_300 */ } else { - val[1] = 0x00; /* Hash */ + val[3] = 0x00; /* Hash */ } } else { if (first_ppc_cpu->env.mmu_model & POWERPC_MMU_V3) { /* V3 MMU supports both hash and radix (with dynamic switching) */ - val[1] = 0xC0; + val[3] = 0xC0; } else { /* Otherwise we can only do hash */ - val[1] = 0x00; + val[3] = 0x00; } } _FDT(fdt_setprop(fdt, chosen, "ibm,arch-vec-5-platform-support", |