diff options
| author | Alistair Francis | 2020-12-16 19:22:26 +0100 |
|---|---|---|
| committer | Alistair Francis | 2020-12-18 06:56:43 +0100 |
| commit | 617448a46b60c353fae0c645a024b628c1f9f700 (patch) | |
| tree | 9a9ba6c916e9e59a6448f94c880902e373cb2f6d /hw/riscv/boot.c | |
| parent | intc/ibex_plic: Clear interrupts that occur during claim process (diff) | |
| download | qemu-617448a46b60c353fae0c645a024b628c1f9f700.tar.gz qemu-617448a46b60c353fae0c645a024b628c1f9f700.tar.xz qemu-617448a46b60c353fae0c645a024b628c1f9f700.zip | |
hw/riscv: Expand the is 32-bit check to support more CPUs
Currently the riscv_is_32_bit() function only supports the generic rv32
CPUs. Extend the function to support the SiFive and LowRISC CPUs as
well.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
Acked-by: Palmer Dabbelt <palmerdabbelt@google.com>
Message-id: 9a13764115ba78688ba61b56526c6de65fc3ef42.1608142916.git.alistair.francis@wdc.com
Diffstat (limited to 'hw/riscv/boot.c')
| -rw-r--r-- | hw/riscv/boot.c | 12 |
1 files changed, 11 insertions, 1 deletions
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index d62f3dc758..3c70ac75d7 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -41,7 +41,17 @@ bool riscv_is_32_bit(MachineState *machine) { - if (!strncmp(machine->cpu_type, "rv32", 4)) { + /* + * To determine if the CPU is 32-bit we need to check a few different CPUs. + * + * If the CPU starts with rv32 + * If the CPU is a sifive 3 seriries CPU (E31, U34) + * If it's the Ibex CPU + */ + if (!strncmp(machine->cpu_type, "rv32", 4) || + (!strncmp(machine->cpu_type, "sifive", 6) && + machine->cpu_type[8] == '3') || + !strncmp(machine->cpu_type, "lowrisc-ibex", 12)) { return true; } else { return false; |