diff options
| author | Bin Meng | 2020-09-03 12:40:13 +0200 |
|---|---|---|
| committer | Alistair Francis | 2020-09-10 00:54:19 +0200 |
| commit | 9fe640a53dd8ef33d32ab6e833fa9b6d1356cfae (patch) | |
| tree | e43324f5eb23319ff3d718d6617feb86d004ddf9 /hw/riscv/meson.build | |
| parent | hw/riscv: Move sifive_e_prci model to hw/misc (diff) | |
| download | qemu-9fe640a53dd8ef33d32ab6e833fa9b6d1356cfae.tar.gz qemu-9fe640a53dd8ef33d32ab6e833fa9b6d1356cfae.tar.xz qemu-9fe640a53dd8ef33d32ab6e833fa9b6d1356cfae.zip | |
hw/riscv: Move sifive_u_prci model to hw/misc
This is an effort to clean up the hw/riscv directory. Ideally it
should only contain the RISC-V SoC / machine codes plus generic
codes. Let's move sifive_u_prci model to hw/misc directory.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1599129623-68957-3-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'hw/riscv/meson.build')
| -rw-r--r-- | hw/riscv/meson.build | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build index 003994d1ea..3462cb5a28 100644 --- a/hw/riscv/meson.build +++ b/hw/riscv/meson.build @@ -12,7 +12,6 @@ riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_uart.c')) riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c')) riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c')) riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u_otp.c')) -riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u_prci.c')) riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('riscv_htif.c')) riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c')) riscv_ss.add(when: 'CONFIG_MICROCHIP_PFSOC', if_true: files('microchip_pfsoc.c')) |