diff options
| author | Bin Meng | 2020-09-03 12:40:19 +0200 |
|---|---|---|
| committer | Alistair Francis | 2020-09-10 00:54:19 +0200 |
| commit | b609b7e3199912e16ef3b0447823f21fed73597e (patch) | |
| tree | a4996e2869a356811e641d243f53347b26117106 /hw/riscv/meson.build | |
| parent | hw/riscv: Move riscv_htif model to hw/char (diff) | |
| download | qemu-b609b7e3199912e16ef3b0447823f21fed73597e.tar.gz qemu-b609b7e3199912e16ef3b0447823f21fed73597e.tar.xz qemu-b609b7e3199912e16ef3b0447823f21fed73597e.zip | |
hw/riscv: Move sifive_uart model to hw/char
This is an effort to clean up the hw/riscv directory. Ideally it
should only contain the RISC-V SoC / machine codes plus generic
codes. Let's move sifive_uart model to hw/char directory.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1599129623-68957-9-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'hw/riscv/meson.build')
| -rw-r--r-- | hw/riscv/meson.build | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build index 90df67acc7..967572d4f6 100644 --- a/hw/riscv/meson.build +++ b/hw/riscv/meson.build @@ -5,7 +5,6 @@ riscv_ss.add(when: 'CONFIG_HART', if_true: files('riscv_hart.c')) riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c')) riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c')) riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_test.c')) -riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_uart.c')) riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c')) riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c')) riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c')) |