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| author | Georg Kotheimer | 2021-03-19 15:14:59 +0100 |
|---|---|---|
| committer | Alistair Francis | 2021-03-23 02:54:40 +0100 |
| commit | ec352d0cab58a7bf66019057d0dfcffd9e7785a8 (patch) | |
| tree | 9a044109c6972d89378f4857a286ca4a478621fb /hw/riscv/microchip_pfsoc.c | |
| parent | target/riscv: Fix read and write accesses to vsip and vsie (diff) | |
| download | qemu-ec352d0cab58a7bf66019057d0dfcffd9e7785a8.tar.gz qemu-ec352d0cab58a7bf66019057d0dfcffd9e7785a8.tar.xz qemu-ec352d0cab58a7bf66019057d0dfcffd9e7785a8.zip | |
target/riscv: Add proper two-stage lookup exception detection
The current two-stage lookup detection in riscv_cpu_do_interrupt falls
short of its purpose, as all it checks is whether two-stage address
translation either via the hypervisor-load store instructions or the
MPRV feature would be allowed.
What we really need instead is whether two-stage address translation was
active when the exception was raised. However, in riscv_cpu_do_interrupt
we do not have the information to reliably detect this. Therefore, when
we raise a memory fault exception we have to record whether two-stage
address translation is active.
Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210319141459.1196741-1-georg.kotheimer@kernkonzept.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'hw/riscv/microchip_pfsoc.c')
0 files changed, 0 insertions, 0 deletions