diff options
| author | Alistair Francis | 2020-10-14 02:17:33 +0200 |
|---|---|---|
| committer | Alistair Francis | 2020-10-22 21:00:22 +0200 |
| commit | 38bc4e34f29b913d28a8d2abcf2bf74a4a4a816e (patch) | |
| tree | b32fdca754d2b62043f812157b1a199075fca2fc /hw/riscv/opentitan.c | |
| parent | hw/riscv: Add a riscv_is_32_bit() function (diff) | |
| download | qemu-38bc4e34f29b913d28a8d2abcf2bf74a4a4a816e.tar.gz qemu-38bc4e34f29b913d28a8d2abcf2bf74a4a4a816e.tar.xz qemu-38bc4e34f29b913d28a8d2abcf2bf74a4a4a816e.zip | |
hw/riscv: Load the kernel after the firmware
Instead of loading the kernel at a hardcoded start address, let's load
the kernel at the next aligned address after the end of the firmware.
This should have no impact for current users of OpenSBI, but will
allow loading a noMMU kernel at the start of memory.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Tested-by: Bin Meng <bin.meng@windriver.com>
Message-id: 46c00c4f15b42feb792090e3d74359e180a6d954.1602634524.git.alistair.francis@wdc.com
Diffstat (limited to 'hw/riscv/opentitan.c')
| -rw-r--r-- | hw/riscv/opentitan.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c index 0531bd879b..cc758b78b8 100644 --- a/hw/riscv/opentitan.c +++ b/hw/riscv/opentitan.c @@ -75,7 +75,8 @@ static void opentitan_board_init(MachineState *machine) } if (machine->kernel_filename) { - riscv_load_kernel(machine->kernel_filename, NULL); + riscv_load_kernel(machine->kernel_filename, + memmap[IBEX_DEV_RAM].base, NULL); } } |