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| author | Bin Meng | 2019-09-06 18:19:58 +0200 |
|---|---|---|
| committer | Palmer Dabbelt | 2019-09-17 17:42:46 +0200 |
| commit | 56449d20e937e807e4fc35fa3e5a38f7636e7046 (patch) | |
| tree | 43aba52df5fbc31c9135873e04506163ddb773e8 /hw/riscv/sifive_e.c | |
| parent | riscv: sifive_u: Remove the unnecessary include of prci header (diff) | |
| download | qemu-56449d20e937e807e4fc35fa3e5a38f7636e7046.tar.gz qemu-56449d20e937e807e4fc35fa3e5a38f7636e7046.tar.xz qemu-56449d20e937e807e4fc35fa3e5a38f7636e7046.zip | |
riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h}
Current SiFive PRCI model only works with sifive_e machine, as it
only emulates registers or PRCI block in the FE310 SoC.
Rename the file name to make it clear that it is for sifive_e.
This also prefix "sifive_e"/"SIFIVE_E" for all macros, variables
and functions.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Chih-Min Chao <chihmin.chao@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Diffstat (limited to 'hw/riscv/sifive_e.c')
| -rw-r--r-- | hw/riscv/sifive_e.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index 792d75a1a3..1428a99fce 100644 --- a/hw/riscv/sifive_e.c +++ b/hw/riscv/sifive_e.c @@ -40,9 +40,9 @@ #include "hw/riscv/riscv_hart.h" #include "hw/riscv/sifive_plic.h" #include "hw/riscv/sifive_clint.h" -#include "hw/riscv/sifive_prci.h" #include "hw/riscv/sifive_uart.h" #include "hw/riscv/sifive_e.h" +#include "hw/riscv/sifive_e_prci.h" #include "hw/riscv/boot.h" #include "chardev/char.h" #include "sysemu/arch_init.h" @@ -174,7 +174,7 @@ static void riscv_sifive_e_soc_realize(DeviceState *dev, Error **errp) SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE); sifive_mmio_emulate(sys_mem, "riscv.sifive.e.aon", memmap[SIFIVE_E_AON].base, memmap[SIFIVE_E_AON].size); - sifive_prci_create(memmap[SIFIVE_E_PRCI].base); + sifive_e_prci_create(memmap[SIFIVE_E_PRCI].base); /* GPIO */ |