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authorMichael Clark2018-03-03 23:52:13 +0100
committerMichael Clark2018-05-06 00:54:21 +0200
commit5aec3247c190f10654250203a1742490ae7343a2 (patch)
tree16cf7f8c792a3e7d4372c4dac507e16888fe293e /hw/riscv/sifive_e.c
parentRISC-V: No traps on writes to misa,minstret,mcycle (diff)
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RISC-V: Mark ROM read-only after copying in code
The sifive_u machine already marks its ROM readonly however it has the wrong base address for its mask ROM. This patch fixes the sifive_u mask ROM base address. This commit makes all other boards consistently use mask_rom as the variable name for their ROMs. Boards that use device tree now check that that the device tree fits in the assigned ROM space using the new qemu_fdt_totalsize(void *fdt) interface, adding a bounds check and error message. This can detect truncation. Cc: Sagar Karandikar <sagark@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Cc: Palmer Dabbelt <palmer@sifive.com> Cc: Alistair Francis <Alistair.Francis@wdc.com> Signed-off-by: Michael Clark <mjc@sifive.com> Reviewed-by: Alistair Francis <Alistair.Francis@wdc.com>
Diffstat (limited to 'hw/riscv/sifive_e.c')
-rw-r--r--hw/riscv/sifive_e.c20
1 files changed, 8 insertions, 12 deletions
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
index 6fa2238185..e4ecb7aa4b 100644
--- a/hw/riscv/sifive_e.c
+++ b/hw/riscv/sifive_e.c
@@ -74,14 +74,6 @@ static const struct MemmapEntry {
[SIFIVE_E_DTIM] = { 0x80000000, 0x4000 }
};
-static void copy_le32_to_phys(hwaddr pa, uint32_t *rom, size_t len)
-{
- int i;
- for (i = 0; i < (len >> 2); i++) {
- stl_phys(&address_space_memory, pa + (i << 2), rom[i]);
- }
-}
-
static uint64_t load_kernel(const char *kernel_filename)
{
uint64_t kernel_entry, kernel_high;
@@ -112,6 +104,7 @@ static void riscv_sifive_e_init(MachineState *machine)
MemoryRegion *main_mem = g_new(MemoryRegion, 1);
MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
MemoryRegion *xip_mem = g_new(MemoryRegion, 1);
+ int i;
/* Initialize SOC */
object_initialize(&s->soc, sizeof(s->soc), TYPE_RISCV_HART_ARRAY);
@@ -131,7 +124,7 @@ static void riscv_sifive_e_init(MachineState *machine)
memmap[SIFIVE_E_DTIM].base, main_mem);
/* Mask ROM */
- memory_region_init_ram(mask_rom, NULL, "riscv.sifive.e.mrom",
+ memory_region_init_rom(mask_rom, NULL, "riscv.sifive.e.mrom",
memmap[SIFIVE_E_MROM].size, &error_fatal);
memory_region_add_subregion(sys_mem,
memmap[SIFIVE_E_MROM].base, mask_rom);
@@ -185,9 +178,12 @@ static void riscv_sifive_e_init(MachineState *machine)
0x00028067, /* 0x1004: jr t0 */
};
- /* copy in the reset vector */
- copy_le32_to_phys(memmap[SIFIVE_E_MROM].base, reset_vec, sizeof(reset_vec));
- memory_region_set_readonly(mask_rom, true);
+ /* copy in the reset vector in little_endian byte order */
+ for (i = 0; i < sizeof(reset_vec) >> 2; i++) {
+ reset_vec[i] = cpu_to_le32(reset_vec[i]);
+ }
+ rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
+ memmap[SIFIVE_E_MROM].base, &address_space_memory);
if (machine->kernel_filename) {
load_kernel(machine->kernel_filename);