diff options
| author | Alistair Francis | 2018-04-26 22:54:12 +0200 |
|---|---|---|
| committer | Alistair Francis | 2018-07-06 00:24:25 +0200 |
| commit | 647a70a10f257bdeba33ff5f1bcb2b26518a9f4c (patch) | |
| tree | 0fcbbc950d37e8599ae8f5cfb9c0e19bf28276e2 /hw/riscv/sifive_e.c | |
| parent | hw/riscv/sifive_e: Create a SiFive E SoC object (diff) | |
| download | qemu-647a70a10f257bdeba33ff5f1bcb2b26518a9f4c.tar.gz qemu-647a70a10f257bdeba33ff5f1bcb2b26518a9f4c.tar.xz qemu-647a70a10f257bdeba33ff5f1bcb2b26518a9f4c.zip | |
hw/riscv/sifive_plic: Use gpios instead of irqs
Instead of creating the interrupt in lines with qemu_allocate_irq() use
qdev_init_gpio_in() as this gives us the ability to use the qdev*gpio*()
helpers later on.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Suggested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Michael Clark <mjc@sifive.com>
Diffstat (limited to 'hw/riscv/sifive_e.c')
| -rw-r--r-- | hw/riscv/sifive_e.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index cb1b6948bf..8a8dbe1c00 100644 --- a/hw/riscv/sifive_e.c +++ b/hw/riscv/sifive_e.c @@ -187,13 +187,14 @@ static void riscv_sifive_e_soc_realize(DeviceState *dev, Error **errp) sifive_mmio_emulate(sys_mem, "riscv.sifive.e.gpio0", memmap[SIFIVE_E_GPIO0].base, memmap[SIFIVE_E_GPIO0].size); sifive_uart_create(sys_mem, memmap[SIFIVE_E_UART0].base, - serial_hd(0), SIFIVE_PLIC(s->plic)->irqs[SIFIVE_E_UART0_IRQ]); + serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_E_UART0_IRQ)); sifive_mmio_emulate(sys_mem, "riscv.sifive.e.qspi0", memmap[SIFIVE_E_QSPI0].base, memmap[SIFIVE_E_QSPI0].size); sifive_mmio_emulate(sys_mem, "riscv.sifive.e.pwm0", memmap[SIFIVE_E_PWM0].base, memmap[SIFIVE_E_PWM0].size); /* sifive_uart_create(sys_mem, memmap[SIFIVE_E_UART1].base, - serial_hd(1), SIFIVE_PLIC(s->plic)->irqs[SIFIVE_E_UART1_IRQ]); */ + serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), + SIFIVE_E_UART1_IRQ)); */ sifive_mmio_emulate(sys_mem, "riscv.sifive.e.qspi1", memmap[SIFIVE_E_QSPI1].base, memmap[SIFIVE_E_QSPI1].size); sifive_mmio_emulate(sys_mem, "riscv.sifive.e.pwm1", |