diff options
| author | Bin Meng | 2020-09-03 12:40:19 +0200 |
|---|---|---|
| committer | Alistair Francis | 2020-09-10 00:54:19 +0200 |
| commit | b609b7e3199912e16ef3b0447823f21fed73597e (patch) | |
| tree | a4996e2869a356811e641d243f53347b26117106 /hw/riscv/sifive_e.c | |
| parent | hw/riscv: Move riscv_htif model to hw/char (diff) | |
| download | qemu-b609b7e3199912e16ef3b0447823f21fed73597e.tar.gz qemu-b609b7e3199912e16ef3b0447823f21fed73597e.tar.xz qemu-b609b7e3199912e16ef3b0447823f21fed73597e.zip | |
hw/riscv: Move sifive_uart model to hw/char
This is an effort to clean up the hw/riscv directory. Ideally it
should only contain the RISC-V SoC / machine codes plus generic
codes. Let's move sifive_uart model to hw/char directory.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1599129623-68957-9-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'hw/riscv/sifive_e.c')
| -rw-r--r-- | hw/riscv/sifive_e.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index 0ddcf1508d..40bbf530d4 100644 --- a/hw/riscv/sifive_e.c +++ b/hw/riscv/sifive_e.c @@ -39,9 +39,9 @@ #include "hw/misc/unimp.h" #include "target/riscv/cpu.h" #include "hw/riscv/riscv_hart.h" -#include "hw/riscv/sifive_uart.h" #include "hw/riscv/sifive_e.h" #include "hw/riscv/boot.h" +#include "hw/char/sifive_uart.h" #include "hw/intc/sifive_clint.h" #include "hw/intc/sifive_plic.h" #include "hw/misc/sifive_e_prci.h" |