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| author | Alistair Francis | 2019-04-04 20:15:23 +0200 |
|---|---|---|
| committer | Palmer Dabbelt | 2019-04-05 01:36:19 +0200 |
| commit | 0feb4a7129eb4f120c75849ddc9e50495c50cb63 (patch) | |
| tree | 47228ddc89549d44f57dba7a5b0ce93455246ff9 /hw/riscv/sifive_plic.c | |
| parent | Update version for v4.0.0-rc2 release (diff) | |
| download | qemu-0feb4a7129eb4f120c75849ddc9e50495c50cb63.tar.gz qemu-0feb4a7129eb4f120c75849ddc9e50495c50cb63.tar.xz qemu-0feb4a7129eb4f120c75849ddc9e50495c50cb63.zip | |
riscv: plic: Fix incorrect irq calculation
This patch fixes four different things, to maintain bisectability they
have been merged into a single patch. The following fixes are below:
sifive_plic: Fix incorrect irq calculation
The irq is incorrectly calculated to be off by one. It has worked in the
past as the priority_base offset has also been set incorrectly. We are
about to fix the priority_base offset so first first the irq
calculation.
sifive_u: Fix PLIC priority base offset and numbering
According to the FU540 manual the PLIC source priority address starts at
an offset of 0x04 and not 0x00. The same manual also specifies that the
PLIC only has 53 source priorities. Fix these two incorrect header
files.
We also need to over extend the plic_gpios[] array as the PLIC sources
count from 1 and not 0.
riscv: sifive_e: Fix PLIC priority base offset
According to the FE31 manual the PLIC source priority address starts at
an offset of 0x04 and not 0x00.
riscv: virt: Fix PLIC priority base offset
Update the virt offsets based on the newly updated SiFive U and SiFive E
offsets.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Diffstat (limited to 'hw/riscv/sifive_plic.c')
| -rw-r--r-- | hw/riscv/sifive_plic.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/hw/riscv/sifive_plic.c b/hw/riscv/sifive_plic.c index ac768e6c27..0315e035e5 100644 --- a/hw/riscv/sifive_plic.c +++ b/hw/riscv/sifive_plic.c @@ -207,7 +207,7 @@ static uint64_t sifive_plic_read(void *opaque, hwaddr addr, unsigned size) if (addr >= plic->priority_base && /* 4 bytes per source */ addr < plic->priority_base + (plic->num_sources << 2)) { - uint32_t irq = (addr - plic->priority_base) >> 2; + uint32_t irq = ((addr - plic->priority_base) >> 2) + 1; if (RISCV_DEBUG_PLIC) { qemu_log("plic: read priority: irq=%d priority=%d\n", irq, plic->source_priority[irq]); @@ -280,7 +280,7 @@ static void sifive_plic_write(void *opaque, hwaddr addr, uint64_t value, if (addr >= plic->priority_base && /* 4 bytes per source */ addr < plic->priority_base + (plic->num_sources << 2)) { - uint32_t irq = (addr - plic->priority_base) >> 2; + uint32_t irq = ((addr - plic->priority_base) >> 2) + 1; plic->source_priority[irq] = value & 7; if (RISCV_DEBUG_PLIC) { qemu_log("plic: write priority: irq=%d priority=%d\n", |