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| author | Alistair Francis | 2020-12-16 19:23:08 +0100 |
|---|---|---|
| committer | Alistair Francis | 2020-12-18 06:56:44 +0100 |
| commit | 3ed2b8ac2dacc22c088ec5793ecde31db2fa0414 (patch) | |
| tree | 734bb793e6c561360a30de8ecca155ebf2db112a /hw/riscv/sifive_u.c | |
| parent | target/riscv: cpu: Set XLEN independently from target (diff) | |
| download | qemu-3ed2b8ac2dacc22c088ec5793ecde31db2fa0414.tar.gz qemu-3ed2b8ac2dacc22c088ec5793ecde31db2fa0414.tar.xz qemu-3ed2b8ac2dacc22c088ec5793ecde31db2fa0414.zip | |
hw/riscv: Use the CPU to determine if 32-bit
Instead of using string compares to determine if a RISC-V machine is
using 32-bit or 64-bit CPUs we can use the initalised CPUs. This avoids
us having to maintain a list of CPU names to compare against.
This commit also fixes the name of the function to match the
riscv_cpu_is_32bit() function.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 8ab7614e5df93ab5267788b73dcd75f9f5615e82.1608142916.git.alistair.francis@wdc.com
Diffstat (limited to 'hw/riscv/sifive_u.c')
| -rw-r--r-- | hw/riscv/sifive_u.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 170e49315f..f5c400dd44 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -466,7 +466,7 @@ static void sifive_u_machine_init(MachineState *machine) /* create device tree */ create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline, - riscv_is_32_bit(machine)); + riscv_is_32bit(s->soc.u_cpus)); if (s->start_in_flash) { /* @@ -495,7 +495,7 @@ static void sifive_u_machine_init(MachineState *machine) break; } - if (riscv_is_32_bit(machine)) { + if (riscv_is_32bit(s->soc.u_cpus)) { firmware_end_addr = riscv_find_and_load_firmware(machine, "opensbi-riscv32-generic-fw_dynamic.bin", start_addr, NULL); @@ -506,7 +506,7 @@ static void sifive_u_machine_init(MachineState *machine) } if (machine->kernel_filename) { - kernel_start_addr = riscv_calc_kernel_start_addr(machine, + kernel_start_addr = riscv_calc_kernel_start_addr(s->soc.u_cpus, firmware_end_addr); kernel_entry = riscv_load_kernel(machine->kernel_filename, @@ -533,7 +533,7 @@ static void sifive_u_machine_init(MachineState *machine) /* Compute the fdt load address in dram */ fdt_load_addr = riscv_load_fdt(memmap[SIFIVE_U_DEV_DRAM].base, machine->ram_size, s->fdt); - if (!riscv_is_32_bit(machine)) { + if (!riscv_is_32bit(s->soc.u_cpus)) { start_addr_hi32 = (uint64_t)start_addr >> 32; } @@ -552,7 +552,7 @@ static void sifive_u_machine_init(MachineState *machine) 0x00000000, /* fw_dyn: */ }; - if (riscv_is_32_bit(machine)) { + if (riscv_is_32bit(s->soc.u_cpus)) { reset_vec[4] = 0x0202a583; /* lw a1, 32(t0) */ reset_vec[5] = 0x0182a283; /* lw t0, 24(t0) */ } else { |