diff options
| author | Bin Meng | 2020-09-03 12:40:16 +0200 |
|---|---|---|
| committer | Alistair Francis | 2020-09-10 00:54:19 +0200 |
| commit | 406fafd5d0f9a1c6a365ff1733c26a043b1c4877 (patch) | |
| tree | ee4ed77217e62a3d3a8c185e8eda59ff2a138c35 /hw/riscv/sifive_u.c | |
| parent | hw/riscv: Move sifive_gpio model to hw/gpio (diff) | |
| download | qemu-406fafd5d0f9a1c6a365ff1733c26a043b1c4877.tar.gz qemu-406fafd5d0f9a1c6a365ff1733c26a043b1c4877.tar.xz qemu-406fafd5d0f9a1c6a365ff1733c26a043b1c4877.zip | |
hw/riscv: Move sifive_clint model to hw/intc
This is an effort to clean up the hw/riscv directory. Ideally it
should only contain the RISC-V SoC / machine codes plus generic
codes. Let's move sifive_clint model to hw/intc directory.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1599129623-68957-6-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'hw/riscv/sifive_u.c')
| -rw-r--r-- | hw/riscv/sifive_u.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 79975372ef..7187d1ad17 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -47,10 +47,10 @@ #include "target/riscv/cpu.h" #include "hw/riscv/riscv_hart.h" #include "hw/riscv/sifive_plic.h" -#include "hw/riscv/sifive_clint.h" #include "hw/riscv/sifive_uart.h" #include "hw/riscv/sifive_u.h" #include "hw/riscv/boot.h" +#include "hw/intc/sifive_clint.h" #include "chardev/char.h" #include "net/eth.h" #include "sysemu/arch_init.h" |