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authorAlistair Francis2020-12-16 19:22:37 +0100
committerAlistair Francis2020-12-18 06:56:44 +0100
commit7893677184681d648165caf9e8a25fccc79b4cf3 (patch)
tree70642cebd297884cd070dc56bab3bd945acc615f /hw/riscv/virt.c
parentriscv: virt: Remove target macro conditionals (diff)
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hw/riscv: boot: Remove compile time XLEN checks
Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Tested-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Acked-by: Palmer Dabbelt <palmerdabbelt@google.com> Message-id: 51e9842dbed1acceebad7f97bd3aae69aa1ac19e.1608142916.git.alistair.francis@wdc.com
Diffstat (limited to 'hw/riscv/virt.c')
-rw-r--r--hw/riscv/virt.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 3e41dbfd3c..5377075869 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -654,7 +654,7 @@ static void virt_machine_init(MachineState *machine)
fdt_load_addr = riscv_load_fdt(memmap[VIRT_DRAM].base,
machine->ram_size, s->fdt);
/* load the reset vector */
- riscv_setup_rom_reset_vec(start_addr, virt_memmap[VIRT_MROM].base,
+ riscv_setup_rom_reset_vec(machine, start_addr, virt_memmap[VIRT_MROM].base,
virt_memmap[VIRT_MROM].size, kernel_entry,
fdt_load_addr, s->fdt);