diff options
| author | Bin Meng | 2020-03-07 13:48:39 +0100 |
|---|---|---|
| committer | Alistair Francis | 2020-04-29 22:16:37 +0200 |
| commit | e883e9927ae667a2473c4a4ec666df53af1b34d9 (patch) | |
| tree | 2e54bbcf182f36f0bf926a7366a00b543315f174 /hw/riscv/virt.c | |
| parent | riscv: Fix Stage2 SV32 page table walk (diff) | |
| download | qemu-e883e9927ae667a2473c4a4ec666df53af1b34d9.tar.gz qemu-e883e9927ae667a2473c4a4ec666df53af1b34d9.tar.xz qemu-e883e9927ae667a2473c4a4ec666df53af1b34d9.zip | |
hw/riscv: Generate correct "mmu-type" for 32-bit machines
32-bit machine should have its CPU's "mmu-type" set to "riscv,sv32".
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1583585319-26603-1-git-send-email-bmeng.cn@gmail.com
Message-Id: <1583585319-26603-1-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'hw/riscv/virt.c')
| -rw-r--r-- | hw/riscv/virt.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 85ec9e22aa..c621a970aa 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -229,7 +229,11 @@ static void create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap, char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); char *isa = riscv_isa_string(&s->soc.harts[cpu]); qemu_fdt_add_subnode(fdt, nodename); +#if defined(TARGET_RISCV32) + qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv32"); +#else qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48"); +#endif qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa); qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv"); qemu_fdt_setprop_string(fdt, nodename, "status", "okay"); |