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| author | Georg Kotheimer | 2020-10-13 19:22:23 +0200 |
|---|---|---|
| committer | Alistair Francis | 2020-10-22 21:00:22 +0200 |
| commit | 1da46012eaaeb2feb3aa6a5a8fc0a03200b673aa (patch) | |
| tree | 10470a252045e34f111eacae67b8d12095138024 /hw/riscv | |
| parent | target/riscv: Fix update of hstatus.GVA in riscv_cpu_do_interrupt (diff) | |
| download | qemu-1da46012eaaeb2feb3aa6a5a8fc0a03200b673aa.tar.gz qemu-1da46012eaaeb2feb3aa6a5a8fc0a03200b673aa.tar.xz qemu-1da46012eaaeb2feb3aa6a5a8fc0a03200b673aa.zip | |
target/riscv: Fix implementation of HLVX.WU instruction
The HLVX.WU instruction is supposed to read a machine word,
but prior to this change it read a byte instead.
Fixes: 8c5362acb57 ("target/riscv: Allow generating hlv/hlvx/hsv instructions")
Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20201013172223.443645-1-georg.kotheimer@kernkonzept.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'hw/riscv')
0 files changed, 0 insertions, 0 deletions