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| author | Bin Meng | 2020-09-03 12:40:21 +0200 |
|---|---|---|
| committer | Alistair Francis | 2020-09-10 00:54:19 +0200 |
| commit | 30a4af1664aa0effdde8db18c92113653befdbdd (patch) | |
| tree | 168f649ab355f4d2a355602f53135c4c966dcee0 /hw/riscv | |
| parent | hw/riscv: Move sifive_test model to hw/misc (diff) | |
| download | qemu-30a4af1664aa0effdde8db18c92113653befdbdd.tar.gz qemu-30a4af1664aa0effdde8db18c92113653befdbdd.tar.xz qemu-30a4af1664aa0effdde8db18c92113653befdbdd.zip | |
hw/riscv: Always build riscv_hart.c
Every RISC-V machine needs riscv_hart hence there is no need to
have a dedicated Kconfig option for it. Drop the Kconfig option
and always build riscv_hart.c.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1599129623-68957-11-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'hw/riscv')
| -rw-r--r-- | hw/riscv/Kconfig | 9 | ||||
| -rw-r--r-- | hw/riscv/meson.build | 2 |
2 files changed, 1 insertions, 10 deletions
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig index 8e0710001b..7d017bc7c3 100644 --- a/hw/riscv/Kconfig +++ b/hw/riscv/Kconfig @@ -1,6 +1,3 @@ -config HART - bool - config IBEX bool @@ -10,7 +7,6 @@ config SIFIVE config SIFIVE_E bool - select HART select SIFIVE select SIFIVE_CLINT select SIFIVE_GPIO @@ -22,7 +18,6 @@ config SIFIVE_E config SIFIVE_U bool select CADENCE - select HART select SIFIVE select SIFIVE_CLINT select SIFIVE_GPIO @@ -35,7 +30,6 @@ config SIFIVE_U config SPIKE bool - select HART select HTIF select SIFIVE select SIFIVE_CLINT @@ -44,7 +38,6 @@ config SPIKE config OPENTITAN bool select IBEX - select HART select UNIMP config RISCV_VIRT @@ -52,7 +45,6 @@ config RISCV_VIRT imply PCI_DEVICES imply TEST_DEVICES select PCI - select HART select SERIAL select GOLDFISH_RTC select VIRTIO_MMIO @@ -65,7 +57,6 @@ config RISCV_VIRT config MICROCHIP_PFSOC bool - select HART select SIFIVE select SIFIVE_CLINT select UNIMP diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build index f762623288..275c0f7eb7 100644 --- a/hw/riscv/meson.build +++ b/hw/riscv/meson.build @@ -1,7 +1,7 @@ riscv_ss = ss.source_set() riscv_ss.add(files('boot.c'), fdt) riscv_ss.add(files('numa.c')) -riscv_ss.add(when: 'CONFIG_HART', if_true: files('riscv_hart.c')) +riscv_ss.add(files('riscv_hart.c')) riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c')) riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c')) riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c')) |