diff options
| author | Alistair Francis | 2021-08-30 07:35:15 +0200 |
|---|---|---|
| committer | Alistair Francis | 2021-09-20 23:56:49 +0200 |
| commit | 57a3a6226529e60ef4eb5e11b577f2e532a72acc (patch) | |
| tree | 26b5f8a9f08a1ea63b22635e2a0c44e0414293f4 /hw/riscv | |
| parent | hw/intc: sifive_plic: Convert the PLIC to use RISC-V CPU GPIO lines (diff) | |
| download | qemu-57a3a6226529e60ef4eb5e11b577f2e532a72acc.tar.gz qemu-57a3a6226529e60ef4eb5e11b577f2e532a72acc.tar.xz qemu-57a3a6226529e60ef4eb5e11b577f2e532a72acc.zip | |
hw/intc: ibex_timer: Convert the timer to use RISC-V CPU GPIO lines
Instead of using riscv_cpu_update_mip() let's instead use the new RISC-V
CPU GPIO lines to set the timer MIP bits.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 84d5b1d5783d2e79eee69a2f7ac480cc0c070db3.1630301632.git.alistair.francis@wdc.com
Diffstat (limited to 'hw/riscv')
| -rw-r--r-- | hw/riscv/opentitan.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c index 048aced0ec..f7cfcf1c3a 100644 --- a/hw/riscv/opentitan.c +++ b/hw/riscv/opentitan.c @@ -183,6 +183,9 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp) sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer), 0, qdev_get_gpio_in(DEVICE(&s->plic), IBEX_TIMER_TIMEREXPIRED0_0)); + qdev_connect_gpio_out(DEVICE(&s->timer), 0, + qdev_get_gpio_in(DEVICE(qemu_get_cpu(0)), + IRQ_M_TIMER)); create_unimplemented_device("riscv.lowrisc.ibex.gpio", memmap[IBEX_DEV_GPIO].base, memmap[IBEX_DEV_GPIO].size); |