diff options
| author | Alistair Francis | 2022-09-14 12:11:07 +0200 |
|---|---|---|
| committer | Alistair Francis | 2022-09-26 23:04:38 +0200 |
| commit | d057aaece7665d49e81ef8d8204b095351253f21 (patch) | |
| tree | a6ccb46f08670502d58bec1dc3db851db750a18e /hw/riscv | |
| parent | target/riscv: Set the CPU resetvec directly (diff) | |
| download | qemu-d057aaece7665d49e81ef8d8204b095351253f21.tar.gz qemu-d057aaece7665d49e81ef8d8204b095351253f21.tar.xz qemu-d057aaece7665d49e81ef8d8204b095351253f21.zip | |
hw/riscv: opentitan: Fixup resetvec
The resetvec for the OpenTitan machine ended up being set to an out of
date value, so let's fix that and bump it to the correct start address
(after the boot ROM)
Fixes: bf8803c64d75 "hw/riscv: opentitan: bump opentitan version"
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220914101108.82571-3-alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'hw/riscv')
| -rw-r--r-- | hw/riscv/opentitan.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c index af13dbe3b1..45c92c9bbc 100644 --- a/hw/riscv/opentitan.c +++ b/hw/riscv/opentitan.c @@ -142,7 +142,7 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp) &error_abort); object_property_set_int(OBJECT(&s->cpus), "num-harts", ms->smp.cpus, &error_abort); - object_property_set_int(OBJECT(&s->cpus), "resetvec", 0x20000490, + object_property_set_int(OBJECT(&s->cpus), "resetvec", 0x20000400, &error_abort); sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_fatal); |