diff options
| author | Bin Meng | 2019-09-06 18:20:00 +0200 |
|---|---|---|
| committer | Palmer Dabbelt | 2019-09-17 17:42:46 +0200 |
| commit | d0730344fd8f27ce5e98efd43efe594ae3a00087 (patch) | |
| tree | 49354c614249153a146acb31a677c9f717055abf /hw/riscv | |
| parent | riscv: sifive_e: prci: Fix a typo of hfxosccfg register programming (diff) | |
| download | qemu-d0730344fd8f27ce5e98efd43efe594ae3a00087.tar.gz qemu-d0730344fd8f27ce5e98efd43efe594ae3a00087.tar.xz qemu-d0730344fd8f27ce5e98efd43efe594ae3a00087.zip | |
riscv: sifive_e: prci: Update the PRCI register block size
Currently the PRCI register block size is set to 0x8000, but in fact
0x1000 is enough, which is also what the manual says.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Chih-Min Chao <chihmin.chao@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Diffstat (limited to 'hw/riscv')
| -rw-r--r-- | hw/riscv/sifive_e_prci.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/hw/riscv/sifive_e_prci.c b/hw/riscv/sifive_e_prci.c index bfe9b13a67..a1c0d44f18 100644 --- a/hw/riscv/sifive_e_prci.c +++ b/hw/riscv/sifive_e_prci.c @@ -87,7 +87,7 @@ static void sifive_e_prci_init(Object *obj) SiFiveEPRCIState *s = SIFIVE_E_PRCI(obj); memory_region_init_io(&s->mmio, obj, &sifive_e_prci_ops, s, - TYPE_SIFIVE_E_PRCI, 0x8000); + TYPE_SIFIVE_E_PRCI, SIFIVE_E_PRCI_REG_SIZE); sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); s->hfrosccfg = (SIFIVE_E_PRCI_HFROSCCFG_RDY | SIFIVE_E_PRCI_HFROSCCFG_EN); |