diff options
| author | Bin Meng | 2020-07-16 11:30:56 +0200 |
|---|---|---|
| committer | Alistair Francis | 2020-07-22 18:39:46 +0200 |
| commit | e79d27cb322b60b460b709d2c74ff7d77cde0565 (patch) | |
| tree | 68cd5478640ed930427eba0646e3bf19b1093e50 /hw/riscv | |
| parent | target/riscv: fix vector index load/store constraints (diff) | |
| download | qemu-e79d27cb322b60b460b709d2c74ff7d77cde0565.tar.gz qemu-e79d27cb322b60b460b709d2c74ff7d77cde0565.tar.xz qemu-e79d27cb322b60b460b709d2c74ff7d77cde0565.zip | |
hw/riscv: sifive_e: Correct debug block size
Currently the debug region size is set to 0x100, but according to
FE310-G000 and FE310-G002 manuals:
FE310-G000: 0x100 - 0xFFF
FE310-G002: 0x0 - 0xFFF
Change the size to 0x1000 that applies to both.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1594891856-15474-1-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'hw/riscv')
| -rw-r--r-- | hw/riscv/sifive_e.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index 7bb97b463d..c8b060486a 100644 --- a/hw/riscv/sifive_e.c +++ b/hw/riscv/sifive_e.c @@ -54,7 +54,7 @@ static const struct MemmapEntry { hwaddr base; hwaddr size; } sifive_e_memmap[] = { - [SIFIVE_E_DEBUG] = { 0x0, 0x100 }, + [SIFIVE_E_DEBUG] = { 0x0, 0x1000 }, [SIFIVE_E_MROM] = { 0x1000, 0x2000 }, [SIFIVE_E_OTP] = { 0x20000, 0x2000 }, [SIFIVE_E_CLINT] = { 0x2000000, 0x10000 }, |