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| author | Alistair Francis | 2022-06-09 01:47:01 +0200 |
|---|---|---|
| committer | Alistair Francis | 2022-06-10 01:42:12 +0200 |
| commit | 07314158f6aa4d2589520c194a7531b9364a8d54 (patch) | |
| tree | f1f508cc436cab122b0d832653b4a27245114597 /hw/rtc | |
| parent | target/riscv: Don't expose the CPU properties on names CPUs (diff) | |
| download | qemu-07314158f6aa4d2589520c194a7531b9364a8d54.tar.gz qemu-07314158f6aa4d2589520c194a7531b9364a8d54.tar.xz qemu-07314158f6aa4d2589520c194a7531b9364a8d54.zip | |
target/riscv: trans_rvv: Avoid assert for RV32 and e64
When running a 32-bit guest, with a e64 vmv.v.x and vl_eq_vlmax set to
true the `tcg_debug_assert(vece <= MO_32)` will be triggered inside
tcg_gen_gvec_dup_i32().
This patch checks that condition and instead uses tcg_gen_gvec_dup_i64()
is required.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1028
Suggested-by: Robert Bu <robert.bu@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220608234701.369536-1-alistair.francis@opensource.wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'hw/rtc')
0 files changed, 0 insertions, 0 deletions