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| author | Anup Patel | 2022-06-16 05:15:42 +0200 |
|---|---|---|
| committer | Alistair Francis | 2022-07-03 02:03:20 +0200 |
| commit | df01af337f0cd48137ec67e207e3de5956acc379 (patch) | |
| tree | 3ada49fa13393b44bf5000363de66b5e548ace99 /hw/rtc | |
| parent | target/riscv: Set minumum priv spec version for mcountinhibit (diff) | |
| download | qemu-df01af337f0cd48137ec67e207e3de5956acc379.tar.gz qemu-df01af337f0cd48137ec67e207e3de5956acc379.tar.xz qemu-df01af337f0cd48137ec67e207e3de5956acc379.zip | |
target/riscv: Remove CSRs that set/clear an IMSIC interrupt file bits
Based on architecture review committee feedback, the [m|s|vs]seteienum,
[m|s|vs]clreienum, [m|s|vs]seteipnum, and [m|s|vs]clreipnum CSRs are
removed in the latest AIA draft v0.3.0 specification.
(Refer, https://github.com/riscv/riscv-aia/releases/tag/0.3.0-draft.31)
These CSRs were mostly for software convenience and software can always
use [m|s|vs]iselect and [m|s|vs]ireg CSRs to update the IMSIC interrupt
file bits.
We update the IMSIC CSR emulation as-per above to match the latest AIA
draft specification.
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220616031543.953776-2-apatel@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'hw/rtc')
0 files changed, 0 insertions, 0 deletions