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authorPhilippe Mathieu-Daudé2018-01-16 14:28:20 +0100
committerPeter Maydell2018-01-16 14:28:20 +0100
commit5efc9016e52596ec054b19bb0ae1d274f77f2a2b (patch)
tree9ac9348b1043178be65b5fd3dcd847124774755a /hw/sd/sdhci.c
parentsdhci: rename the SDHC_CAPAB register (diff)
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sdhci: fix CAPAB/MAXCURR registers, both are 64bit and read-only
running qtests: $ make check-qtest-arm GTESTER check-qtest-arm SDHC rd_4b @0x44 not implemented SDHC wr_4b @0x40 <- 0x89abcdef not implemented SDHC wr_4b @0x44 <- 0x01234567 not implemented Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Message-id: 20180115182436.2066-12-f4bug@amsat.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/sd/sdhci.c')
-rw-r--r--hw/sd/sdhci.c23
1 files changed, 19 insertions, 4 deletions
diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
index c4e486e2ff..d4fcebcd6a 100644
--- a/hw/sd/sdhci.c
+++ b/hw/sd/sdhci.c
@@ -899,10 +899,16 @@ static uint64_t sdhci_read(void *opaque, hwaddr offset, unsigned size)
ret = s->acmd12errsts;
break;
case SDHC_CAPAB:
- ret = s->capareg;
+ ret = (uint32_t)s->capareg;
+ break;
+ case SDHC_CAPAB + 4:
+ ret = (uint32_t)(s->capareg >> 32);
break;
case SDHC_MAXCURR:
- ret = s->maxcurr;
+ ret = (uint32_t)s->maxcurr;
+ break;
+ case SDHC_MAXCURR + 4:
+ ret = (uint32_t)(s->maxcurr >> 32);
break;
case SDHC_ADMAERR:
ret = s->admaerr;
@@ -1123,6 +1129,15 @@ sdhci_write(void *opaque, hwaddr offset, uint64_t val, unsigned size)
}
sdhci_update_irq(s);
break;
+
+ case SDHC_CAPAB:
+ case SDHC_CAPAB + 4:
+ case SDHC_MAXCURR:
+ case SDHC_MAXCURR + 4:
+ qemu_log_mask(LOG_GUEST_ERROR, "SDHC wr_%ub @0x%02" HWADDR_PRIx
+ " <- 0x%08x read-only\n", size, offset, value >> shift);
+ break;
+
default:
qemu_log_mask(LOG_UNIMP, "SDHC wr_%ub @0x%02" HWADDR_PRIx " <- 0x%08x "
"not implemented\n", size, offset, value >> shift);
@@ -1163,8 +1178,8 @@ static inline unsigned int sdhci_get_fifolen(SDHCIState *s)
#define DEFINE_SDHCI_COMMON_PROPERTIES(_state) \
/* Capabilities registers provide information on supported features
* of this specific host controller implementation */ \
- DEFINE_PROP_UINT32("capareg", _state, capareg, SDHC_CAPAB_REG_DEFAULT), \
- DEFINE_PROP_UINT32("maxcurr", _state, maxcurr, 0)
+ DEFINE_PROP_UINT64("capareg", _state, capareg, SDHC_CAPAB_REG_DEFAULT), \
+ DEFINE_PROP_UINT64("maxcurr", _state, maxcurr, 0)
static void sdhci_initfn(SDHCIState *s)
{